A.V. Bashkirov

2026

1. Application of graph neural networks to optimize clock tree synthesis in architectures with programmable logic Radioengineering, No. 7, 2026 pp. 67-71

2025

1. Organization of a decoding system using a partially parallel architecture Radioengineering, No. 7, 2025 pp. 20-24
2. Application of deep neural networks for the task of channel estimation and signal detection in systems with OFDM Radioengineering, No. 7, 2025 pp. 10-14

2024

1. Improving the efficiency of channel evaluation during high-speed data transmission in underwater acoustic communication with OFDM Radioengineering, No. 7, 2024 pp. 45-49

2023

1. Application of the method of equivalent message encoding structures to simplify coding complexity Radioengineering, No. 8, 2023 pp. 16-20

2022

1. Development of QC-LDPC decoder with high capacity for 5G wireless radio Radioengineering, No. 7, 2022 pp. 14-19
2. The problem of radiation stability of subthreshold reference circuits for space radio electronics Radioengineering, No. 7, 2022 pp. 10-13

2021

1. Methods for improving the main characteristics of class d high-frequency amplifiers Radioengineering, No. 6, 2021 pp. 62-66
2. Stochastic iterative decoder Radioengineering, No. 6, 2021 pp. 12-16

2020

1. Improving belief propagation on graphs with cycles Radioengineering, No. 6, 2020 pp. 37-41
2. Analysis of symbol error rate for 16-QAM signals in the presence of QPSK and 16-QAM signals Radioengineering, No. 6, 2020 pp. 5-9

2019

1. Stochastic iterative decoding on factor graphs Radioengineering, No. 6, 2019 pp. 112-126
2. Problems of interaction and compatibility of systems smart home with peripheral devices Radioengineering, No. 6, 2019 pp. 113-116
3. Time-frequency analysis of non-stationary signals by wavelet-transform and windowed Fourier transform methods Radioengineering, No. 6, 2019 pp. 109-112
4. Application of quantization to reduce the decoding difficulty of LDPC codes Radioengineering, No. 6, 2019 pp. 105-108

2018

1. Fpga-based design and implementation of a multifunctional LDPC decoder Radioengineering, No. 7, 2018 pp. 46-51
2. The application of the method of tracking forecast memory to reduce the complexity of hardware implementation of stochastic decoders Radioengineering, No. 7, 2018 pp. 25-28

2017

1. Implementation quantization scheme messages for NB-LDPC decoder on FPGA Radioengineering, No. 6, 2017 pp. 184-189
2. Design and implementation of FPGA to regular (2, DC) NB-LDPC decoders Radioengineering, No. 6, 2017 pp. 179-183

2016

1. Overview of error-correcting coding of digital data communucation systems Radioengineering, No. 6, 2016 pp. 31-35
2. Algorithms low complexity decoding and architecture for non-binary low density codes Radioengineering, No. 6, 2016 pp. 10-14
3. Configurable architecture decoder for QC-LDPC code Radioengineering, No. 6, 2016 pp. 6-9
4. Low-density codes low power decode Radioengineering, No. 5, 2016 pp. 32-37
5. Algorithms for fast decoding LDPC-code in GF(q) Radioengineering, No. 5, 2016 pp. 26-31

2014

1. Implementation of Viterbi decoding on massively parallel computing devices Radioengineering, No. 11, 2014 pp. 20-24
2. Architectural features radeon graphics processors family and their application in the field of resource-intensive simulations of error-correcting codecs Radioengineering, No. 11, 2014 pp. 15-18
3. Defect analysis and thermal characteristics decoder FPGA in their design and manufacture Radioengineering, No. 6, 2014 pp. 74-77
4. Prospects of use of OFDM-modulation in multi-PLC network. Standards PLC-technologies Radioengineering, No. 6, 2014 pp. 70-73
5. Using LDPC-codes. Applications, advantages and prospects Radioengineering, No. 3, 2014 pp. 77-79
6. Construction of algorithms functional verification decoder model Radioengineering, No. 3, 2014 pp. 72-76
7. Possibilities of application non-binary block and convolutional error correction codes Radioengineering, No. 3, 2014 pp. 59-61

2013

1. Overview of the main technologies that implement effective methods of error-correcting coding insensitive to signal delay Radioengineering, No. 12, 2013 pp. 30-33
2. Perspectives of parameters simulation of error-correcting coding algorithms with a high degree of parallelism using a hardware platform based on GPU Radioengineering, No. 12, 2013 pp. 26-29
3. Overview of the main technologies that implement effective methods of error-correcting coding, signal delay-sensitive Radioengineering, No. 3, 2013 pp. 89-92

2012

1. Principle assert for the decision of tasks of search of mistakes RTL a code at designing FPGA Radioengineering, No. 8, 2012 pp. 74-76
2. Analysis methods for turbocodes in the challenges of hardware implementation Radioengineering, No. 8, 2012 pp. 70-74
3. Analysis of energy noiseless coding algorithms Radioengineering, No. 8, 2012 pp. 67-70
4. The Problem of High-Performance Error-Correcting Coding Digital Signals when Implemented on FPGAs Radioengineering, No. 2, 2012 pp. 28-31