Design and implementation of FPGA to regular (2, DC) NB-LDPC decoders
- 1 Ph. D. (Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
- 2 Dr. Sc. (Eng.), Professor, Head of Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
- 3 Post-graduate Student, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University
Abstract
This paper describes variable node with a low-latency processing with the use of the algorithm skimming, together with the advanced min-sum check node processing with low latency by prefetching and relaxing redundancy control.
How to cite
Башкиров А.В., Муратов А.В., Хорошайлова М.В. Архитектура и реализация на ПЛИС регулярных (2, dc) NB-LDPC-декодеров // Радиотехника. 2017. № 6. С. 179–183.
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