Principle assert for the decision of tasks of search of mistakes RTL a code at designing FPGA

This article discusses the possibility of applying the principle of verification assert in an environment that allows for detection of errors in the RTL code. The increasing complexity of microelectronic engineering project outputs in the first place the problem of functional verification in the overall development cycle and verification of electronic products. Approximately half of the engineering staff, working on large projects, functional verification is busy, and time spent on it in the general design cycle took more than 60% of the time the design of systems on a chip. The peculiarity of the functional verification of SoC is the presence of both digital and analog parts, which greatly complicates the process of creating test sequences for verification of quality performance newly developed project. The requirements in the choice of algorithms and mathematical models for the verification environment, namely:

- Algorithms must provide high coverage verification code as it is one of the main indicators of the quality of verification;

- The model should have sufficient flexibility and adequacy;

- Algorithms and models must be economically justified in terms of time and resources for their implementation.

- High speed, since for complete verification of floating point arithmetic units on the IEEE-754 standard requires the run of about 10 million test vectors; independence from the simulation environment, support the main producers of verification platforms.