A.V. Bashkirov1, M.V. Khoroshailova2, A.S. Demikhova3, E.V. Tyretskaya4

1-4 FSBEI of HE “Voronezh State Technical University” (Voronezh, Russia)

1 fabi7@mail.ru; 2 pmv2205@mail.ru; 3 kipr@vorstu.ru, 4 kipr@vorstu.ru

Problem statement. Clock tree synthesis (CTS) in FPGAs determines the performance and power consumption of computing modules. The existing methods are focused on the uniform distribution of the clock signal and do not take into account the specifics of architectures with sequential activation of modules, which leads to excessive energy consumption and increased desynchronization, especially in systems with distributed control based on the "token ring" principle. The use of graph neural networks (GNNs) is proposed to adapt the clock tree to the topology of the marker ring, predict optimal buffer placement points and configuration of gating elements with a ranking of the significance of connections to minimize desynchronization without increasing computational costs, which will increase the energy efficiency and fault tolerance of on-board computing modules of the UAS.

Goal. Development of a method for optimizing the synthesis of clock trees for architectures with programmable logic based on graph neural networks, taking into account the features of distributed control with the transfer of access rights and ensuring a reduction in power consumption and desynchronization of clock signals in onboard UAS systems.

Practical significance. The use of graph neural networks with a mechanism for ranking the significance of connections automates the search for optimal buffer placement points and configuration of gating elements, reducing the burden on the designer and reducing synthesis time, providing a compromise between clock quality, power consumption and design time for energy-efficient onboard UAS systems based on programmable logic.

The work was carried out with the financial support of the Ministry of Science and Higher Education of the Russian Federation within the framework of the state assignment "youth laboratory" № FZGM-2024-0003

Bashkirov A.V., Khoroshailova M.V., Demikhova A.S., Tyretskaya E.V.  Organization of a decoding system using a partially parallel architecture // Radiotekhnika. 2026. V. 90. № 7. P. 67−71. DOI: https://doi.org/10.18127/j00338486-202607-12

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