Journals
Books
Articles by keyword logic synthesis
Models and methods of synthesis of technological processes
A.E. Nikitin, V.P. Rumyantsev, А.V. Trusov
Self-timed shift register implementation according to synchronous counterpart Verilog-description

Yu.A. Stepchenkov1, Yu.G. Diachenko2, D.V. Khilko3, D.Yu. Stepchenkov4, D.Yu. Diachenko5, B.A. Stepanov6

1–6 Federal Research Center «Computer Science» of the Russian Academy Science (Moscow, Russia)
1 YStepchenkov@ipiran.ru, 2 diaura@mail.ru, 3 dhilko@yandex.ru, 4 stepchenkov@mail.ru, 5 diaden87@gmail.com, 6 gtx360@mail.ru