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Regulation of Logic Gate Characteristics for Fully Depleted SOI CMOS Nanotransistors
N.V. Masalsky
Low power 1-bit full adder characteristics for fully depleted SOI CMOS nanotransistors
N.V. Masalsky
Vertical CMOS nanotransistors with a conical channel for three-dimensional integrated circuits

Н.В. Masalsky1

1 Federal State Institution "Scientific Research Institute for System Analysis of RAS" (Moscow, Russia)

Variations in the characteristics of low-voltage logic gates based on vertical silicon nanotransistors with a conical channel

N.V. Masalsky1

1 Research Institute for Systems Research of the Russian Academy of Sciences (Moscow, Russia)
volkov@niisi.ras.ru