Н.В. Masalsky1

1 Federal State Institution "Scientific Research Institute for System Analysis of RAS" (Moscow, Russia)

The issues of numerical simulation of low-voltage logic gates based on silicon vertical CMOS nanotransistors with a surrounding gate with a conical working area for three-dimensional integrated circuits are discussed. The use of the shape of the working area in the form of a truncated cone in comparison with the usual cylindrical shape improves the electrophysical characteristics and allows you to compensate for the limitations that arise as a result of scaling. The shape of the cone is set as follows. From the source side for a large diameter, the condition for suppressing short-channel effects is not met, and from the drain side for a small diameter, it is fulfilled. Numerical studies of conical prototypes were carried out using mathematical modeling performed using the TCAD instrument technological modeling program based on 3D models of n- and p-types of nanotransistors developed by TCAD in this work. The simulation results demonstrate that the electrophysical characteristics of the conical structure in the control voltage range from 0 to 0.6 V are characterized by a higher transistor current, a maximum Ion/Ioff current ratio, a low leakage current and a slope of the subthreshold characteristic close to the theoretical aisle. For an optimized ratio of the diameters of the working area of 7.9/9.6 nm and the length of the working area of 22 nm, the 3D architecture of the inverter and adder modulo 2, consisting of vertically arranged transistors of n- and p-types, is studied. 3D TCAD models of devices have been developed and their electro-physical characteristics have been numerically investigated at control voltages of 0.6 V and a frequency of 25 GHz. The inverter model predicts a maximum switching delay of 1.3 ps, the maximum level of active power of 0.2 MW, static 5 MW. The adder model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 0.82 MW, static 20.2 MW. The promising characteristics of the proposed transistors, such as a high degree of integration, high performance (high speed and low power consumption) and low cost, open the way to the development of 3D integrated circuits of the next generation.

Masalsky Н.В. Vertical CMOS nanotransistors with a conical channel for three-dimensional integrated circuits. Electromagnetic waves and electronic systems. 2022. V. 27. № 4. P. 64−72. DOI: https://doi.org/10.18127/j15604128-202204-09 (in Russian)

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