N.V. Masalsky1

1 Research Institute for Systems Research of the Russian Academy of Sciences (Moscow, Russia)
volkov@niisi.ras.ru

The issues of numerical simulation of fluctuations in the electro-physical characteristics of low-voltage logic gates based on silicon vertical nanotransistors with a surrounding gate with a conical geometry are discussed. Instrumentation and technological models of n- and p-types of conductivity of conical nanotransistors have been developed for the case when the conical working area is set as follows. On the source side, for a large diameter, the condition for suppressing short-channel effects is not fulfilled, and on the drain side, for a small diameter, it is fulfilled. Such transistor structures in the control voltage range from 0 to 0.6 V are characterized by a higher transistor current, a low leakage current and a slope of the subthreshold characteristic close to the theoretical limit. Prototypes of transistors with optimal parameters for the synthesis of logic gates with a gate length of 25 nm and a working area diameter ratio of 8.5/10 nm have been selected. The fluctuation range of the drain current is distributed according to the normal law for both types of transistors with an average of 12.25 µA for the n-type and 6.5 µA for the p-type and a standard deviation of 19.3. The total spread is 3.06 µA and 1.45 µA, or 25% and 22%, respectively. To offset the influence of the considered mechanisms, it is recommended to limit the level of doping of the drain/source regions and use relatively large cross-sections of the working area from the range of possible ones. This will ensure stable electro-physical characteristics of transistors with high parry of short-channel effects.

An instrument-technological model of an inverter based on vertically arranged n- and p-type transistors with an optimized diameter ratio has been developed. Variations of electro-physical characteristics in the range of control voltages 0...0.6 V and a clock frequency of 20 GHz are numerically investigated. In all cases, the prototypes demonstrate picosecond delays and low power consumption. The valve model predicts a general fluctuation of switching times of 18% at average values of 1.6 and 0.8 ps, respectively, active power of 16% at an average value of 0.2 µW and static power of 11% at an average value of 0.7 pW.

The results of the study can be used in the design of digital circuits to expand the SOA zone.

Masalsky N.V. Variations in the characteristics of low-voltage logic gates based on vertical silicon nanotransistors with a conical channel. Nanotechnology: development and applications – XXI century. 2024. V. 16. № 3. P. 31–40. DOI: https://doi.org/10.18127/ j22250980-202403-04 (in Russian)

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