J.A. Zhivchikova1

1 FSUE RFNC «All-Russian Research Institute of Experimental Physics» (Sarov, Russia)
1 zhivchik96@mail.ru

When developing custom physical verification systems for analog integrated circuit topologies, the issue of confirming the correctness and reliability of the results of the developed algorithms is a pressing one. A thorough, iterative testing and debugging process is the key to creating a high-quality tool that eliminates software errors during design.

Objective: to create a methodology for testing software products for physical verification of our own design.

A testing methodology was developed based on automated coordinate-by-coordinate comparison of the results of an algorithmic framework for DRC and LVS verification developed in-house with the results of a reference CAD system, which are considered as a benchmark. A test framework was developed from synthetic and industrial examples-integrated circuit topology fragments and the results of the reference CAD system's operation on them. The methodology was validated using the developed test framework. Various error classes were identified in the in-house DRC and LVS algorithms. Performance characteristics of the reference CAD algorithms were revealed. Development assumptions were formulated based on the testing results. The proposed approach is integrated into the infrastructure for developing tools for the physical verification of analog integrated circuit topologies.

Zhivchikova J.A. Domestic IC physical verification system. Testing method // Achievements of modern radioelectronics. 2026. V. 80. № 8. P. 51–58. DOI: https://doi.org/10.18127/j20700784-202608-07

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