Physical Characteristics SOI of Transistors for Nanoelectronics

In the International Technology Roadmap for Semiconductors, low dimensional structures, such as semiconductor nanowires, are explicitly mentioned as realistic constructions. Devices based on such structures are, however, still in an embryonic stage from an industrial point of view. Whether they will really have an impact on future post-complementary metaloxide-semiconductor (CMOS) technology depends on more factors. From the history of the semiconductor industry, we have learned that only those technologies that can scaled up for large hierarchical systems will survive and have impact (VLSI). To integrate nanowires into electronic components reliably, a thorough understanding of their relevant physical properties is required. The well-established physics of low dimensional semiconductor materials must be revised for the specific one-dimensional nanowire properties, such as surface and interface relaxation, carrier confinement (electrons and holes), and the strong dielectric index change at the nanowire environment interface. These new theories must be compared with experiments on actual nanowire structures.

This review is divided into seven sections, each addressing important steps toward the implementation of semiconductor nanotechnologies. The first section (Introduction) characterizes a modern condition of the semi-conductor industry. The second and third section (2 and 3) describes tasks related to understanding conductivities, and electron transport nanowires, ultimately controlling, various aspects of nanowire growth. This is followed by a section (4) discussing the development and optimization of new, nano channel -specific processing techniques. After that (in section 5), we briefly cover the importance of characterizing, modeling, and extracting important physical properties in order to evaluate and optimize SOI nanotransistors and processing. The simple models of nanotransistors then need to be identified, and characterized, which is briefly described in the next (6) section. The last section (7) is summary deals with integration and up-scaling issues of SOI structures.