Yu.A. Stepchenkov1, Yu.G. Diachenko2, N.V. Morozov3, G.A. Orlov4, D.Yu. Diachenko5, G.S. Appolonov6

1–6 Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences (Moscow, Russia)
1 YStepchenkov@frccsc.ru, 2 YDyachenko@frccsc.ru, 3 NMorozov@frccsc.ru,
4 GOrlov@frccsc.ru, 5 DDyachenko@frccsc.ru, 6 GAppolonov@frccsc.ru

Self-timed (ST) circuits, while offering several advantages over traditional synchronous circuits, differ significantly in their design. Eliminating the use of a global clock signal requires a more careful design of the control circuit for the ST circuit's functional block's interaction and ensuring all their properties, including parallel dynamic writing to memory units: triggers, registers, counters, etc. Self-timed circuits require detection and acknowledgement of the successful completion of all actions with information signals within the circuit, including writing the memory cells' state. Unlike the ST circuit initialization upon power-up or circuit restart, which is typically performed asynchronously, without acknowledging successful completion of the initial setup, dynamic writing requires indication of its completion. Binary counters constitute a significant subclass of digital devices in synchronous and ST circuitry. Dynamic writing of a new state based on a logical condition is often used in them to implement a specified conversion factor or organize the next period of counting the monitored event number. This article addresses the ST circuit design automation problem and, in particular, the implementation of binary reversible ST counters with ST writing. Its goal is to develop a method and typical circuit designs that ensure the efficient synthesis of binary reversible ST counters with dynamic ST write counter state. The results described in the paper include a method for composing a multi-bit reversible ST counter with functional parts implementing the required properties, a procedure for new state ST writing, and a four-bit version of this ST counter. The functional blocks (fragments) used for counter composing are as follows: a parallel bit-by-bit write input driver, a counting direction trigger, an ST counter core with counting mode indication, and an indication subcircuit. The counter's environment implements ST write and counting direction change during the working phase. The proposed ST write procedure's circuit implementation is invariant to the number of the counter's bits and the counting direction. The described construction method enables algorithmic and automated synthesis of the reversible ST counters during an ST circuit automated design. The article reveals the specifics of the reversible ST counter circuit implementation and proposes a method for ST-based writing of a new state to a counter. Practical application of the proposed method and the functional part's circuit designs of a reversible ST counter will facilitate and accelerate their development based on a library of ready-made parameterized templates.

Stepchenkov Yu.A., Diachenko Yu.G., Morozov N.V., Orlov G.A., Diachenko D.Yu., Appolonov G.S. Reversible self-timed counter implementation // Highly Available Systems. 2026. V. 22. № 3. P. 37−44. DOI: https://doi.org/10.18127/j20729472-202603-04

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