Yu.G. Diachenko

Ю.Г. Дьяченко

5 articles 2023–2026

Highly available systems 5

2026

Reversible self-timed counter implementation Highly available systems, No. 3, 2026 pp. 37-44

2025

Self-timed shift register implementation according to synchronous counterpart Verilog-description Highly available systems, No. 3, 2025 pp. 58-68

2024

Novel FPGA clock concept and dual-mode basic logic element Highly available systems, No. 2, 2024 pp. 56-64

2023

Self-timed circuits design automation Highly available systems, No. 3, 2023 pp. 48-56
Self-timed pipeline optimization Highly available systems, No. 1, 2023 pp. 5-13