N.V. Masalsky

2026

1. A method of highly sensitive pH sensing based on a silicon combined ion-sensitive nanotransistor Biomedical Radioelectronics, No. 4, 2026 pp. 99-110

2025

1. An effective method of pH-metry based on a complementary scheme of ion-sensitive nanotransistors Biomedical Radioelectronics, No. 3, 2025 pp. 60-69

2024

1. Variations in the characteristics of low-voltage logic gates based on vertical silicon nanotransistors with a conical channel Nanotechnology : the development , application - XXI Century, No. 3, 2024 pp. 31-40

2022

1. Sensory properties of a complementary pair of silicon field-effect nanotransistors with cylindrical geometry Biomedical Radioelectronics, No. 6, 2022 pp. 67-75
2. Vertical CMOS nanotransistors with a conical channel for three-dimensional integrated circuits Electromagnetic Waves and Electronic Systems, No. 4, 2022 pp. 64-72
3. - Nanotechnology : the development , application - XXI Century, No. 2, 2022 pp. 56-60

2021

1. Sensory properties of fin surrounding gate nanotransistors Electromagnetic Waves and Electronic Systems, No. 6, 2021 pp. 37-43
2. Silicon non-uniformly doped nanotransistor biosensors Science Intensive Technologies, No. 4, 2021 pp. 66-75

2020

1. Silicon non-uniformly doped nanotransistor biosensors Nanotechnology : the development , application - XXI Century, No. 3, 2020 pp. 29-38
2. Nanoscale silicon field effect transistors for biosensors Biomedical Radioelectronics, No. 2, 2020 pp. 74-79

2016

1. Threshold characteristics of the double gate symmetric MOSFETs nanotransistor with a Gaussian vertical doping profile Наноматериалы и наноструктуры - XXI век, No. 1, 2016 pp. 45-51

2014

1. Simulation of the potential temperature distribution in SOI CMOS nanotransistors with «no overlap» architecture Наноматериалы и наноструктуры - XXI век, No. 4, 2014 pp. 9-13

2011

1. Minimizing Short Channel Effects to Performance of Double Gate-Underlap Design SOI CMOS Nanotransistors Electromagnetic Waves and Electronic Systems, No. 11, 2011 pp. 41-47

2010

1. Low power 1-bit full adder characteristics for fully depleted SOI CMOS nanotransistors Electromagnetic Waves and Electronic Systems, No. 4, 2010 pp. 52-56
2. SIMULATIONOFCHARACTERISTICS OF LOGIC GATE AND ARITHMETIC UNITS FOR FULLY DEPLETED SOI CMOS NANOTRANSISTORS Наноматериалы и наноструктуры - XXI век, No. 2, 2010 pp. 9-16

2009

1. Problems of Scaling of CMOS VLSI Characteristics Achievements of Modern Radioelectronics, No. 7, 2009 pp. 3-27
2. Regulation of Logic Gate Characteristics for Fully Depleted SOI CMOS Nanotransistors Electromagnetic Waves and Electronic Systems, No. 6, 2009 pp. 56-62

2008

1. The Mechanisms, determining fluctuations of threshold voltages of short-channel CMOS transistors Achievements of Modern Radioelectronics, No. 7, 2008