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Articles 71

1. Improving efficiency of turbo code decoding by reducing the decoder's sensitivity to information bit values Information-measuring and Control Systems, No. 3, 2026 pp. 67-75
2. Hardware implementation of first-order Reed-Muller decoder with soft output Radioengineering, No. 3, 2026 pp. 139-149
3. Hypernet development for short block code decoders Radioengineering, No. 7, 2025 pp. 57-61
4. Reconfigurable low-density decoder for multi-level wireless local area networks Radioengineering, No. 8, 2023 pp. 94-99
5. Development of QC-LDPC decoder with high capacity for 5G wireless radio Radioengineering, No. 7, 2022 pp. 14-19
6. Priority queue architecture for sequential decoder of polar codes for implementation in hardware Radioengineering, No. 12, 2021 pp. 139-152
7. Neural decoders for quantum codes Radioengineering, No. 6, 2021 pp. 17-22
8. Stochastic iterative decoder Radioengineering, No. 6, 2021 pp. 12-16
9. Fpga-based design and implementation of a multifunctional LDPC decoder Radioengineering, No. 7, 2018 pp. 46-51
10. The application of the method of tracking forecast memory to reduce the complexity of hardware implementation of stochastic decoders Radioengineering, No. 7, 2018 pp. 25-28
11. Minimizing the memory capacity of the decoder's cognitive map in the search for equivalent codes Radioengineering, No. 6, 2018 pp. 38-41
12. Implementation quantization scheme messages for NB-LDPC decoder on FPGA Radioengineering, No. 6, 2017 pp. 184-189
13. Design and implementation of FPGA to regular (2, DC) NB-LDPC decoders Radioengineering, No. 6, 2017 pp. 179-183
14. Software implementation of multithreshold decoders on GPU Radioengineering, No. 11, 2016 pp. 90-96
15. Adaptive data processing simulation in the system with soft decoder Radioengineering, No. 9, 2016 pp. 40-43
16. Configurable architecture decoder for QC-LDPC code Radioengineering, No. 6, 2016 pp. 6-9
17. Defect analysis and thermal characteristics decoder FPGA in their design and manufacture Radioengineering, No. 6, 2014 pp. 74-77
18. Construction of algorithms functional verification decoder model Radioengineering, No. 3, 2014 pp. 72-76
19. Negation of the decoder Neurocomputers, No. 11, 2013 pp. 59-63
20. Complexity reducing method of DB-CRSC turbodecoder Radioengineering, No. 3, 2013 pp. 11-16