A. I. Gushchin1, N. N. Udalov2, D. E. Lashchyov3
1,3 JSC “Russian Space Systems” (Moscow, Russia)
1,2 National Research University “MPEI” (Moscow, Russia)

1 sanyok.centr@yandex.ru, 2 UdalovNN@mpei.ru, 3 Lashev777@gmail.com

In all-digital phase-locked loops (ADPLLs), the main structural blocks such as a phase detector, a low-pass filter, and a voltage-controlled oscillator are implemented digitally. Frequency synthesizers manufactured on the basis of these systems have a significant frequency range from units to tens of gigahertz, low power consumption reaching units of milliwatts and small overall dimensions. Due to these advantages, frequency synthesizers based on ADPLLs can be widely used in satellite communications, radiolocation, and other high-speed applications. However, the development of such synthesizers is difficult due to a number of reasons, the main of which is the lack of a model suitable for tuning synthesizer parameters. Therefore, the problem of creating this model is extremely actual at the present time.

The goal of this article is to design a simulation model of an ADPLL and measure its main characteristics. In previous publications it has been proposed to create models based on functional blocks that do not depict the circuitry of devices. In this article we suggest a simulation model of an ADPLL based on digital logic elements that are closer to a real electronic component base. The proposed model consists of a reference oscillator, a phase-frequency detector, a time-to-digital converter (TDC), a digital loop filter (DLF), a digitally-controlled oscillator (DCO) and a frequency divider.

To ensure the requirements for dynamics and stability the order and coefficients of the DLF operating with the use of the “moving average” method have been determined. After that, other parameters of the structure under consideration have been recalculated using the analogy method between an ADPLL and a phase-locked loop with a charge-pump circuit. The bit depth of the TDC, DLF, and the word controlling the DCO has been also selected.

As a result of the simulation, waveforms have been taken at the main nodes of the circuit and frequencies and levels of the main and the side spectral components at the output of a digitally-controlled oscillator have been measured. The performed research will be useful in designing frequency synthesizers based on an ADPLL. The parameters of the devices being developed will be adjusted based on the simulation results in order to improve their various characteristics.

Gushchin A.I., Udalov N.N., Lashchyov D.E. Simulation model of an all-digital phase-locked loop // Antennas. 2026. № 4. P. 78–85. DOI: https://doi.org/10.18127/j03209601-202604-08

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