2014
- Implementation of Viterbi decoding on massively parallel computing devices pp. 20-24
- Architectural features radeon graphics processors family and their application in the field of resource-intensive simulations of error-correcting codecs pp. 15-18
- Massively parallel computing in a heterogeneous system for modeling low-density codecs pp. 43-46
- Problems of modeling error-correcting codec in heterogeneous systems pp. 80-82
- Construction of algorithms functional verification decoder model pp. 72-76
- Possibilities of application non-binary block and convolutional error correction codes pp. 59-61
2013
- Overview of the main technologies that implement effective methods of error-correcting coding insensitive to signal delay pp. 30-33
- Perspectives of parameters simulation of error-correcting coding algorithms with a high degree of parallelism using a hardware platform based on GPU pp. 26-29
- Overview of the main technologies that implement effective methods of error-correcting coding, signal delay-sensitive pp. 89-92