350 rub
Journal Science Intensive Technologies №11 for 2013 г.
Article in number:
Importance of Layer-to-Layer Deprocessing of Chips for the Failure Analysis of State-of-Art Integrated Circuits
Keywords: chip topological layers failure integrated circuits
Authors:
V.A. Burobin - Ph.D. (Eng.), General Director, GZ Pulsar. E-mail: burobin@gz-pulsar.ru, openline@gz-pulsar.ru
R.А. Milovanov - Research Scientist, MSTU MIREA. E-mail: Milovanov_r@inbox.ru
А.А. Shchuka - Dr.Sc. (Eng.), Professor, MSTU MIREA. E-mail: shchuka@mail.mipt.ru
Abstract:
For analysis of the failure of the state-of-art ICs and revealing the cause of catastrofic breakdown of the chip interconnections layer-to-layer deprocessing plays a significant role. Basic methods that can be used to remove the topological layer are plasma-chemical etching, wet etching, ion-beam etching (IBE) and microgrinding. Each method has its benefits and disadvantages. While choosing a particular deprocessing method for a particular layer, characteristics of underlying layers must be considered. A topological layer can be removed stepwise with different techniques. For example, after removal of aluminium conductors through plasma-chemical etching a surface planarization with help of microgrinding or IBE is required. Characteristics of topological layers and availability of technological tools must be therefore considered when defining a methodology complex to deprocess a definite chip.
Pages: 45-49
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