A.V. Korolev, S.G. Rykov

«JSC All-Russian Scientific Research Institute of Radio Engineering»

This paper is devoted to investigation of DDS phase noise dependency on clock frequency and DDS output signal frequency. The basic block diagram of DDS comprises a phase accumulator, a phase to amplitude converter, a digital to analog converter (DAC). The present phase noise analysis is performed for extended block diagram, in which clock receiving and distribution circuitry is added. Analysis also takes into account DDS output white phase noise which is in versely proportional to sin(x)/x DDS output response. 

This approach made it possible to obtain formulae, which demonstrate that it is possible to eliminate the influence of fluctuations of input buffer threshold voltage when clock frequency decreases. If the value of input voltage slew rate (SR) is unchanged, flicker phase noise of DDS output is independent of DDS clock frequency but is determined only by the DDS output frequency. In this case, the clock waveform may not be sinusoidal. Computer simulations and experiments where performed for three types of contemporary DDS: AD9912, AD9915 from Analog Devices and 1508PL8Т from "ELVEES" R&D CENTER. For these DDS, the coefficients of formulae where experimentally determined. Measurements were performed with signal source analyzer E5052. The clock generator consists of high-precision crystal oscillator with low phase noise harmonic generator. At offset frequencies above 100 Hz phase noise of clock generator has practically no effect on DDS output phase noise. 

Simulations and experiments demonstrate that with high clock frequency, DDS output flicker and fundamental phase noise is mainly caused by fluctuations of clock distribution circuitry delay time and DAC bit currents switching time, whereas when clock frequency is low the main contribution in flicker and fundamental phase noise is made by input buffer threshold voltage fluctuations. Experiments with two types of DDS also confirm negligible change in flicker phase noise when SR is kept constant when the clock frequency changes eight times. For different combinations of clock and output frequencies, the experimental results demonstrate that DDS output white phase noise can exceed input buffer and DAC fundamental noises both at comparatively low fundamental  output frequencies and at image output frequencies close to clock frequency multiples. Good compliance of experimental results and simulations makes resulting formulae applicable for design of frequency synthesizers.

Korolev A.V., Rykov S.G. DDS phase noise dependency on clock frequency and DDS output signal frequency. Radiotekhnika. 2021.  V. 85. № 5. P. 100−116. DOI: https://doi.org/10.18127/j00338486-202105-10 (In Russian)

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