A.E. Krylov1, A.V. Rashich2

1,2 Peter The Great St. Petersburg Polytechnic University (Saint-Petersburg, Russia)

This paper presents VLSI architecture for stack or priority queue (PQ) are required in the implementation or sequential decoder of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work, low latency and low complexity parallel hardware architecture is presented for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.

Krylov A.E., Rashich A.V. Priority queue architecture for sequential decoder of polar codes for implementation in hardware. Radiotekhnika. 2021. V. 85. № 12. P. 139−152. DOI: https://doi.org/10.18127/j00338486-202112-12 (In Russian)

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