A.V. Bashkirov – Ph.D.(Eng.), Associate Professor, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University

E-mail: fabi7@mail.ru

M.V. Horoshaylova – Post-graduate Student, Department of Radio Equipment Engineering and Manufacturing, Voronezh State Technical University

E-mail: pmv2205@mail.ru

This article describes the development of a high-speed architecture for decoding LDPC code for (3,6) -regular codes, using hybrid quantization, pipelining, and optimizing FPGA-specificity. The described pipeline architecture completely meets the significant requirements of the I / O decoder, even if an early termination scheme is used. The proposed decoder can reach throughput up to 16.9 Gbit / s at Eb/N0 3.5 dB using a code of length 1152, operating at a clock speed of 153 MHz and performing a maximum of 10 iterations of decoding, which greatly exceeds the level of technology. This design was fully implemented and tested on FPGA Xilinx Virtex 5 XC5VLX110. It also presents an alternative design with low complexity, which achieves a throughput of up to 21.6 Gb / s, sacrificing 0,75 dB in the definition of Eb/N0.

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