V.I. Kuraedov1

1 National Research University "Moscow Institute of Electronic Technology" (Moscow, Russia)

1 vladimir96k@mail.ru

Comprehensive integrated circuit (IC) verification plays a crucial role in preventing costly errors and delays in product development cycle. It includes testing interaction and compatibility of different system elements, such as central processing unit, memory and various peripheral devices. Validating IC’s compliance to the functional requirements list may take up to 70% of the design process duration. This proportion grows with complexity and size of the device under development. Consequently, the essential tasks that integrated circuit developers face are research and development of methods for cut-ting design complexity and reducing implementation time. Exploration of feasibility of machine learning methods for ATPG process optimization during circuit design has been conducted. An artificial intelligence model based on a stacked sparse autoencoder (SSAE) is being proposed. The use of such a type of AI targets discovering errors, impacting final products’ functionality, in a timely manner. An alternative route for stuck-at-0 и stuck-at-1 type faults discovery is addressed, optimizing its feature reduction through experimental manual adjustment of hidden neuron layers. Comparison data has been gathered between simple AE and SSAE, collected on eight ISCAS’85 combinational circuits. An optimal sparsity constraint has been defined experimentally for maximal SSAE performance. It has been proven that from an accuracy standpoint SSAE out-performs simple AE at 99.5% vs. 98.7% reconstruction precision for the C5315 circuit. Accumulated results allow for the algorithm usage during IC design in order to reduce time consumption for circuitry validation and improve on test kits quality.

Kuraedov V.I. Application of machine learning methods for automatic test pattern generation process optimization during circuit design. Neurocomputers. 2024. V. 26. № 1. Р. 14-22. DOI: https://doi.org/10.18127/j19998554-202401-02 (In Russian)

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