N.I. Chervyakov - Dr.Sc. (Eng.), Professor, Head of Department of the Applied Mathematics and Mathematical Modeling, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol) E-mail: k-fmf-primath@stavsu.ru M.G. Babenko - Ph.D. (Phys.-Math.), Associate Professor, Department of the Applied Mathematics and Mathematical Modeling, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol) E-mail: k-fmf-primath@stavsu.ru A.N. Tchernykh - PhD, Full Professor in the Computer Science Department, Head of the Parallel Computing Laboratory in CICESE Research Center, Ensenada, Baja California, Mexico E-mail: chernykh@cicese.mx V.A. Kuchukov - Post-graduate Student, Department of Applied Mathematics and Mathematical Modeling, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol) E-mail: viktor-kuchukov@yandex.ru M.A. Deryabin - Lecturer Assistant, Department of Applied Mathematics and Mathematical Modeling; Junior Research Scientist, Laboratory of Mathematical Modeling and Theoretical-Numeric Systems, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol) E-mail: maderiabin@ncfu.ru N.N. Kuchukova - Post-graduate Student, Department of Applied Mathematics and Mathematical Modeling, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol) E-mail: knn.storage@yandex.ru

The paper proposes a new neural network method for computing the modular multiplication based on finding by the approximate method remainder of the division by a given module in residue number system (RNS) and the neural network of the final ring. RNS allows to compute addition and multiplication in parallel computing channels without caries between the channels, which increases the speed of arithmetic operations. The paper reviews the algorithms for computing modular multiplication in RNS, that allow to perform modular multiplication without using the operation of finding the remainder of division in the general case, but require precomputing and storage of constants. Considered in the paper modification of Montg omeryalgorithm of modular mul-tiplication is reduced to a simple multiplication with accumulation, where the word length equals to the length of the module, which allows a device to have a fully parallel architecture where each module is associated with one of the modules from RNS moduli set. Approximate method doesn-trequire expensive modular operations, which are replaced by fast right bit shifts and taking lower bits. The paper presents the implementation of finding the remainder of division by a prime number in RNS, in which there is no need to perform computations with whole parts of real numbers, which makes it possible to make the transition from the calculations with fractional parts to integer calculations. Effective implementation of the proposed method using a neural network of the finite ring can increase the speed operations. Algorithms of modular operations correspond too pe-rations with basic processing elements (artificial neurons). FPGA is the perfect element base for the implementation of such parallel structures as a neural network. FPGA allows to implement n parallel neural networks, and the communication between the neurons takes place within the same FPGA at high speed. In addition, the use of a neural network of finite ring (NNFR) reduces the number of cascaded circuits, which allows to increase the speed of information processing. With restriction to arithmetic operations NNFRis more effective in comparison with the binary arithmetic. Since computations with real numbers in FPGA areresource-consuming, the transition from the real numbers to integers, according to the proposed algorithm can significantly increase the speed of data processing. Results of simulation on Kintex7 XC7K70T showed that the proposed method ison average 75 % faster, and takes 80 % less in the area than the modified method from [2], which makes it more useful for hardware implementation of cryptographic primitives over a finite field.

 

1. Manochehri K., Sadeghian B., Pourmozafari S. A modified radix-2 Montgomery modular multiplication with new recoding method // IEICE Electronics Express. 2010. V. 7. № 8. P. 513-519.
2. Choi S.-H., Lee K.-J. New systolic modular multiplication architecture for efficient Montgomery multiplication // IEICE Electronics Express. 2014, V. 12. № 2. P. 2014-1051.
3. Choi S.-H., Lee, K.-J. Enhancement of a modified radix-2 Montgomery modular multiplication // IEICE Electronics Express. 2014. V. 11. № 19. P. 2014-0782.
4. Zivaljevic D., Stamenkovic N., Stojanovic V. Digital filter implementation based on the RNS with diminished-1 encoded channel // Telecommunications and Signal Processing (TSP), 35th International Conference // IEEE. 2012. July. P. 662-666.
5. Yatskiv V., Jun S., Yatskiv N., Sachenko A., Osolinskiy O. Multilevel method of data coding in WSN. // IDAACS, IEEE 6th International Conference. 2011. P. 863-866.
6. Chervyakov N.I., Babenko M.G., Lyakhov P.A., Lavrinenko I.N. An Approximate method for comparing modular numbers and its application to the division of numbers in residue number systems // Cybernetics and Systems Analysis. 2014. V. 50. № 6. P. 977-984.
7. Schinianakis D., Stouraitis T. Multifunction residue architectures for cryptography // Circuits and Systems I: Regular Papers. IEEE Transactions. 2014. V. 61. № 4. P. 1156-1169.
8. Montgomery P. L. Modular multiplication without trial division // Mathematics of computation, 1985. V. 44. № 170. P. 519-521.
9. Schinianakis D., Stouraitis T. A RNS Montgomery multiplication architecture // Circuits and Systems (ISCAS). IEEE International Symposium. 2011. P. 1167-1170.
10. Galushkin A.I. Teorija nejjronnykh setejj. M.: INRZHR. 2000. 416 s.
11. CHervjakov N.I., Sakhnjuk P.A., SHaposhnikov V.A., Makokha A.N. Nejjrokompjutery v ostatochnykh klassakh. Kn. 11. M.: Radiotekhnika. 2003. 272 s.
12. Zhang D. Parallel designs for Chinese remainder conversion // International Conference on Parallel Processing - ICPP. 1987. P. 557-559.
13. Zhang D. Parallel VLSI Neural System Designs. Berlin, Germany: Springer-Verlag. 1998. 257 p.
14. Zang D. Jullien G.A., Miller W.C. A neural-like approach to finite ring computation // IEEE Transactions on Circuits and Systems. 1990. V. 37. № 8. P. 1048-1052.
15. Zhang D., Jullien G.A., Miller W.C. VLSI implementations of neural-like networks for finite ring computations // Proceedings of the 32nd Midwest Symposium on Circuits and Systems. 1989. V.1. P. 485-488.
16. Patent № 2317584 RF. Konvejjernaja nejjronnaja set konechnogo kolca / N.I. CHervjakov. 2008.
17. Patent № 2279132 RF. Nejjronnaja set konechnogo kolca / N.I. CHervjakov, V.A. Galkina, JU.A. Strekalov, S.V. Lavrinenko. 2006.