N.I. Chervyakov - Dr.Sc. (Eng.), Professor, Head of Department of the Applied Mathematics and Mathematical Modeling, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol). E-mail: k-fmf-primath@stavsu.ru P.A. Lyakhov - Ph.D. (Phis.-Math.), Assistant Professor, Department of the Applied Mathematics and Mathematical Modeling, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol). E-mail: ljahov@mail.ru N.F. Semyonova - Ph.D. (Phis.-Math.), Assistant Professor, Department of the Algebra and Geometry, Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol). E-mail: nfsemyonova@mail.ru M.V. Valueva - Master student in «Applied Mathematics and Informatics», Institute of Mathematics and Natural Sciences, North Caucasus Federal University (Stavropol). E-mail: mriya.valueva@mail.ru

The residue number system (RNS) can be effectively used in applications with a predominant share of the operations of addition, subtraction, and multiplication due to lack of carries and parallel execution of operations, thus reducing the time required. So, at present the problem of converting numbers from binary to RNS is relevant. In this study we consider converting numbers to the residue number system with the special moduli set . Getting the remainder of the modulo is a simple task, and an effective solution for a module can be obtained by using parallel-prefix adders. Adders are basic circuits that perform operations of addition of binary numbers and are part of a more complex digital circuits. This paper discusses several types of adders, implementing the addition of two binary numbers: carry propagate ad-ders, carry save adders, parallel-prefix adders and end-around carry adders. The simulation was performed in the environment ISE Design Suite 14.7. Its purpose was to compare the scheme for calculating the remainder of the modulo with using parallel adders and build-in function mod for a 16-bit number, and n varying from 3 to 8. The simulation results showed that using parallel adders increase the speed around 3 times, than using the build-in function mod. Hardware costs for and reduced to 22 times, for up to 20 times, for and up to 10 times and for up to 9 times. It may be concluded that the use of adders with parallel architecture allows to reach high speed and reduce hardware costs for numbers conversion from binary number system to RNS.

 

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