N.V. Masalski - Ph.D. (Phys.-Math.), Senior Researcher, Research Institute for System Studies of RAS, Moscow. E-mail: volkov@niisi.ras.ru

The simulation of the potential distribution in a wide temperature range for dual-gate SOI nanotransistors architecture with \"no overlap\" of gate and drain / source, formed in the form of elongated regions, is performed. Characteristics of nanostructure at small-signal approximation with uniform dopant distribution in its workspace are analyzed. Charge separation approach in the transistor working areas under the electrical neutrality condition in the transistor is used. Discussed analytical model has shown good agreement between numerical results and simulation ones. The proposed model can be used in the development of SOI nanotransistor chips to evaluate their behavior at different temperatures.

 

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