N.V. Masalsky

Ultra-thin-body SOI (silicon-on-insulator) nanotransistors are one of the most promising candidates for future low power and high performance applications. The problems of synthesis of low-voltage characteristics of digital devices made of fully depleted SOI CMOS nanotransistors in the domain of power supply voltage less than 1 V are considered. The design implements through varied values of the back gate voltage of transistors. For the inverter the analytical evaluations of steepness of a control characteristic and adjustment range are obtained. Thus the steepness is determined by relation of thicknesses of frontal and back gates of transistors. The more this relation is the more effective adjustment the get. The relation of delay to displacement on the back gate has linear nature for analyzed power supply voltage range. With decreasing of power supply voltage the adjustment range of delay is narrowed down, however steepness remains practically constant. Generally the logic gate NOR2 steepness of a control characteristic is the greatest, and that for the inverter NAND2 is the smallest. The opportunity of management of a transistor threshold voltage allows as on the one hand, to increase speed of the circuit without increase in active capacity, with another to reduce static capacity. For the adder at a choice of corresponding displacement on the back gate transistors is achieved as 25 % the increase in speed or 22 multiple decrease in static power. At reduction of power supply voltage the decreasing of adjustment range of delay for all investigated elements has non-linear nature. From simulation results if follows that the minimum of product «delay  energy of switching» is reached in the area of power supply voltage less than 1 V. It-s position does not depend on a gate logical function. For the adder its position does not depend on a set of entrance signals. The carried out research allows us to draw a conclusion on an opportunity of development of effective low-voltage difficult devices for fully depleted SOI CMOS nanotransistors.