D.A. Derevyanko - ost-graduate Student, National Research Nuclear University MAPHI (Moscow Engineering Physics Institute). E-mail: nrndda@gmail.com I.I. Shagurin - Dr.Sc. (Eng.), Professor, National Research Nuclear University MAPHI (Moscow Engineering Physics Institute). E-mail: ishagurin@inbox.ru

This article describes application of homogeneous matrices IP blocks for filtering digital signals. In the introduction main difficulties in filtering signals and possible solutions are presented. One solution is the author\'s architecture, which is based on the idea of homogeneous reconfigurable computing structures with a number of important characteristics: flexibility in changing the order of calculations when changing the problem to be solved; a wide range of performing mathematical calculations. Main aspects of constructing homogeneous matrix of multipliers with accumulation and flexible chaining calculations are taken into consideration. Computational elements are described and an example of their work for one calculation step is given. At the end of the second chapter interconnections selection peculiarities in the matrices are given for the optimal use of all computing elements. In addition, the authors examined the main filtering algorithms in described architecture and justify the choice of the multiplier-accumulator as a basis for processing element. To test the architecture of homogeneous matrices, the authors built a FIR filter with filter order 17, 35 and 70 points in conjunction with the IIR filter 1st and 2nd order and a matched filter with filter order from 128 points to 1024 points and the correlation with the same order. At the end of the article proposed architecture and hardware multipliers block are compared, and was shown a slight difference in size, but a significant gain in flexibility of the author\'s architecture.

 

1. Ajjficher EH., Dzhervis B. Cifrovaja obrabotka sirnalov: prakticheskijj podkhod. Izd-e 2-e: Per. s anrl. M.: Izdatelskijj dom «Viljams», 2004. 992 s.
2. Bogner R., Konstantinidis A. Vvedenie v cifrovuju filtraciju: Per. s anrl. M.: Mir. 1976. 216 s.
3. KHamukhin A.A. Rekonfigurirovanie odnorodnojj vychislitelnojj struktury s neprogrammiruemymi jachejjkami dlja reshenija differencialnykh uravnenijj v chastnykh proizvodnykh // Izvestija Tomskogo politekhnicheskogo universiteta. 2010. T. 316. № 5.
4. Kaljaev I.A., Levin I.I., Semernikov E.A., SHmojjlov V.I. Rekonfiguriruemye multikonvejjernye vychislitelnye struktury. 2008. 393 s.
5. JAnakova E.S. Issledovanie i razrabotka metodov cifrovojj soglasovannojj filtracii radiolokacionnykh signalov v geterogennykh sistemakh na kristalle: Diss. kand. tekh. n. 2009. 183 s.
6. Trishin V.N., Lukin N.A. Realizacija diskretnogo preobrazovanija Fure na vychislitelnojj odnorodnojj srede // Doklady VMezhdunar. konf. «Parallelnye vychislenija i zadachi upravlenija». Moskva. 2010.
7. Das A., Rodrigues R., Koren I., Kundu S. A study on performance benefits of core morphing in an asymmetric multicore processor // Computer Design (ICCD). 2010 IEEE International Conference on. 3-6 Oct. 2010. R. 17, 22,
8. Kopta D., Spjut J., Brunvand E., Davis A. Efficient MIMD architectures for high-performance ray tracing // Computer Design (ICCD). IEEE International Conference on. 3-6 Oct. 2010. R. 9, 16.
9. Niiyama K., Ichijo K., Narita A., Yoshioka Y. Execution time measurement of a vector operation on LSC-Based DSP // Intelligent Signal Processing and Communications Systems. ISPACS 2008. International Symposium on. 8-11 Feb. 2009. R. 1, 4, 8.
10. Shenoi B.A. Introduction to digital signal processing and filter design. Published by John Wiley & Sons, Inc. Hoboken. New Jersey. 2006.
11. Attri S., Sohi B.S., Chopra Y.C. Efficient design of application specific DSP cores using FPGAs. ASIC. 2001. Proceedings. 4th International Conference on. 2001. R. 462, 466.
12. Kamalizad A., Tabrizi N., Bagherzadeh N., Hatanaka A. A Programmable DSP Architecture for Wireless Communication Systems // Proceedings of the 16th International Conference on Application-Specific Systems, Architecture and Processors. IEEE. 2005.
13. Bayoumi M.A. VLSI architectures for DSP applications: current trends // Circuits and Systems. 1992. Proceedings of the 35th Midwest Symposium on. 9-12 Aug 1992. V. 1. R. 150,153.
14. Jeong H., Sug H., Myung H., Seung K. Novel DSP Architecure for OFDM Modem Systems // School of Electrical and Computer Engineering. Ajou University. IEEE. 2003.
15. Sachin B., Nikhil N. A Novel High Speed FPGA Architecture for FIR Filter Design // International Journal of Reconfigure and Embedded Systems. March 2012. V. 1. № 1. R. 1-10.