S. F. Tyurin - Dr.Sc. (Eng.), Professor, Perm National Research Polytechnic University. Е-mail: tyurinsergfeo@yandex.ru
A. Yu. Gorodilov - Research Scientist, Perm National Research Polytechnic University. Е-mail: gora830@yandex.ru
A. A. Baydarov - Ph.D. (Eng.), Research Scientist, Perm National Research Polytechnic University. Е-mail: cchp@bk.ru

Modeling of a logical element of the programmable logical integrated schemes (PLIS) of FPGA (field-programmable gate array) ? LUT (Look Up Table) with offered control devices of calculations set by control of configuration memory of SRAM (Static Random Access Memory) of logical functions is described. LUT modeling with four adjusting entrances is carried out in the environment of NI Multisim. In the course of calculation of the set logical function in a tree of transferring LUT transistors for established on entrances And, In, With, the D set one of chains from an entrance on an exit is activated and from the cell of SRAM corresponding to this set value of function via the output inverter is established at the OUT element exit. The assessment of redundancy of a tree of transferring transistors is made. Modeling of logical elements with control of ChLUT-2 is executed and schemes of realized models are submitted. Operability of the offered scheme by a way modeling of working control of a tree of LUT on the example of n = 2 by use of the second, uninvolved on this set of entrance variables is proved to a half of transferring transistors.