350 rub
Journal Information-measuring and Control Systems №8 for 2013 г.
Article in number:
Hardware-levelbarriersynchronization implementation formesh-connected multicomputers
Keywords: mesh-connected multicomputers parallel processes barrier synchronization hardware
Authors:
I.V. Zotov, A.A. Burmaka, R.V. Bredikhin, Yu.O. Sukhochev
Abstract:
The development and investigation of hardware-level methods for barrier synchronization between parallel processes residing in multicomputers is a crucial focus during several last years. The usage of a virtual bit-slice coordinating environment distributed between the processors of a multicomputer such that it provides fast barrier state signal interchange with no limitation on the barrier group configuration and/or the total count of barriers in a parallel program is a prospective research domain. In the present paper, the principals of organization of barrier synchronization between parallel processes in arbitrary dimension mesh-connected multicomputersbased on the usage of a virtual bit-slice coordinating environment are formulated. The environment topology construction rules are stated together with the virtualization principals aimed at the elimination of the limitations on the co-residing barrier count. Virtual slice switch ordering scheme that makes it possible to establish a parallel-pipelined barrier control binary signal interchange mode is sketched. The coordinating environment clocking mechanism is featured which takes into account the presence of a set of virtual slices.
Pages: 41-45
References

  1. MPI: A Message-Passing Interface Standard, Version 3.0 / Message Passing Interface Forum. September 21, 2012. http://www.mpi-forum.org/docs/docs.html
  2. Tsafrir D. and Feitelson D.G. Barrier synchronization on a loaded SMP using two-phase waiting algorithms // Proc. Int-l Parallel Distrib. Processing Symp. 2002. R. 80-87.
  3. Li J., Martinez J.F. and Huang M.C. The thrifty barrier: energy-aware synchronization in shared-memory multiprocessors // Proc. 10th Int-l Symp. HighPerformanceComputerArchitecture. 2004. R. 14-23.
  4. Tzeng N.-T., Kasula B. and Wu Hongyi. Efficient barrier synchronization on wireless computing systems // Proc. 11th Int-l Conf. Paral. Distrib. Systems. 2005. R. 782-788.
  5. Moh S., Yu C., Lee B., Youn H.Y., Han D. and Lee D. Four-ary tree-based barrier synchronization for 2D meshes without nonmember involvement // IEEE Trans. Comput. 2001. V. 50. № 8. R. 811-823.
  6. Hindam T. Connecting the distributed hardware agents for barrier synchronization operation // Proc. Int-l Conf. Electrical, Electronic and Computer Engineering. 2004. R. 261-264.
  7. Sampson J., González R., Collard J.-F., Jouppi N.P., Schlansker M. and Calder B. Exploitingfine-grained data parallelism with chip multiprocessors and fast barriers // Proc. 39th Annual IEEE/ACM Int-l. Symp. Microarchitecture. 2006. R. 235-246.
  8. Delgado M. and Kofuji S. A Distributed Barrier Synchronization Solution in Hardware for 2D-Mesh Multicomputers // Proc. 3rd Int-l Conf. HighPerformanceComputing. 1996. R. 368-373.
  9. Ramakrishnan V., Scherson I.D. and Subramanian R. Efficient techniques for nested and disjoint barrier synchronization // J. Paral. Distrib. Comput. 1999. V. 58. № 8. R. 333-356.
  10. Cohen W.E., Hyde D.W. and Gaede R.K. An optical bus-based distributed dynamic barrier mechanism // IEEE Trans. Comput. 2000. V. 49. № 12. R. 1354-1365.
  11. Johnson T.A. and Hoare R.R. Cyclical cascade chains: a dynamic barrier synchronization mechanism for multiprocessor systems // Proc. 15th Int-l Paral. Distrib. ProcessingSymp. 2001. R. 2061-2068.
  12. Zotov I.V. Distributed virtual bit-slice synchronizer: a scalable hardware barrier mechanism for n-dimensional meshes // IEEE Transactions on Computers. 2010. V. 59. № 9. P. 1187-1199.
  13. Titov V.S., Konoval'chik A.P., Titenko E.A. Vy'sokoproizvoditel'ny'e vy'chislitel'ny'e sistemy' na osnove PLIS // Izvestiya Jugo-Zapadnogo gos. un-ta. 2012. № 4(43). Ch. 2 S. 73-77.