I.A. Sokolov1, S.F. Tyurin2, Yu.A. Stepchenkov3, Yu.G. Diachenko4, M.S. Nikitin5, S.I. Sovetov6

1,3,4 FRC “Computer Science and Control” of RAS (Moscow, Russia)
2,5,6 Perm National Research Polytechnic University (Perm, Russia)
1 ISokolov@ipiran.ru, 2 tyurinsergfeo@yandex.ru, 3 YStepchenkov@ipiran.ru,
4 diaura@mail.ru, 5 mann1k@yandex.ru, 6 fizikoz@gmail.com

Typically, field programmable gate arrays (FPGAs) use a clock generator, which frequency is calculated based on the worst-case transient. Asynchronous circuits operate on real transient delays, but their design is much more complex. Self-timed (ST) circuits, proposed by D. Muller in the late 50s of the twentieth century, the asynchronous circuit subclass, have built-in means of the transition process completion acknowledging. Thanks to this property, ST circuits are characterized by a wide range of performance in terms of supply voltage and ambient temperature and ensure reliable operation at any logic cell delays determined by the current operating conditions. There are currently no commercially available self-timed FPGAs on the market. And numerous attempts to use traditional synchronous FPGAs and their design tools to create self-timed prototypes have not made it possible to fully realize their potential advantages. This article aims to improve the ST circuit FPGA-implementation efficiency. The Institute of Informatics Problems of the Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences is the major center of competence in the self-timed direction in the Russian Federation. On the topic of joint scientific research with the Perm National Research Polytechnic University, a number of logical cells for ST-FPGA have been previously developed.

Target. Formulation of the new FPGA type concept using the operating mode choice, clarification of the proposed logical element's structure and methods of its reconfiguration for a given operating mode, and features of cascading elements of this type for the construction of multi-bit logical elements.

The concept of a new type of FPGA with increased flexibility and operating mode selection is proposed. It allows developers to select not only functions and connections, but also to build digital circuits cases with different operating modes using computer-aided design systems: both synchronous and self-timed, or a combination of both. The design of a dual-mode logic element and details of its reconfiguration, as well as scaling issues for bit capacity increase, are also clarified.

The practical use of the proposed two-mode basic logic element increases the flexibility of digital equipment projects on FPGAs, which is especially important for critical application areas at the current stage of integrated technology development in the Russian Federation.

Sokolov I.A., Tyurin S.F., Stepchenkov Yu.A., Diachenko Yu.G., Nikitin M.S., Sovetov S.I. Novel FPGA clock concept and dual-mode basic logic element. Highly Available Systems. 2024. V. 20. № 2. P. 56−64. DOI: https://doi.org/10.18127/j20729472-202402-04 (in Russian)

1. Muller D.E., Bartky W.S. A theory of asynchronous circuits. On the Theory of Switching. Part 1. Harvard: University Press. 1959. P. 204–243.
2. Aperiodicheskie avtomaty. Pod red. V.I. Varshavskogo. M.: Nauka. 1976. S. 304 (in Russian).
3. Marakhovsky V.B., Surkov A.V. Globally asynchronous system of interactive Moore state machines. IET Computers and Digital Techniques. 2016. V. 10. Is. 4. P. 186–192.
4. Skornyakova A.Yu (Plotnikova A.Yu.) Fault-Tolerant Self-Timed Indicator. Proceedings of the 2016 IEEE North West Russia Section Young Researchers in Electrical and Electronic Engineering Conference, EIConRusNW 2016. 2016. P. 308–312. DOI: 10.1109/EIConRusNW.2016.7448181.
5. Skornyakova A.Yu., Vikhorev R.V. Self-Timed LUT Layout Simulation. Conference of Russian Young Researchers in Electrical and Electronic Engineering. IEEE. 2020. P. 176–179. DOI: 10.1109/EIConRus49466.2020.9039374.
6. Ivanova K.M., Skornyakova A.Yu. Algoritm optimizacii komplekta konfiguriruemyh strogo samosinhronnyh generatorov logicheskih funkcij dlya zadannyh parametrov sistem funkcij. Nanoindustriya. 2020. T. 13. № S4(99). S. 334–336. DOI: 10.22184/1993-8578.2020.13.4s.334.336 (in Russian).
7. Strogonov A., Cybin S. Programmiruemaya kommutaciya PLIS: vzglyad iznutri [Elektronnyj resurs]. URL: http://www.kit-e.ru/articles /plis/2010_11_56.php (data obrashcheniya: 19.06.2024) (in Russian).
8. Patent US № 4870302 XILINX INC. Ross Freeman. Configurable electrical circuit having configurable logic elements and configurable interconnects. Feb 19. 1988.
9. Vikhorev R. Universal logic cells to implement systems functions. Conference of Russian Young Researchers in Electrical and Electronic Engineering. IEEE. 2016. P. 404–406. DOI: 10.1109/EIConRusNW.2016.7448197.
10. Vikhorev R. Improved FPGA logic elements and their simulation. Conference of Russian Young Researchers in Electrical and Electronic Engineering. IEEE. 2018. P. 275–280. DOI: 10.1109/EIConRus.2018.8317080.
11. Speedster22i Configuration User Guide [Elektronnyj resurs]. URL: https://www.achronix.com/sites/default/files/docs/Speedster22i_ Configuration_User_Guide_UG033_v1.3.pdf (data obrashcheniya: 19.06.2024).
12. Otchet o NIR (promezhutochnyj) «Konceptual'nye i metodologicheskie osnovy sozdaniya semejstva potokovyh samosinhronnyh processorov i sredstv podderzhki ih proektirovaniya». Kn. 2. № g.r. AAAA-A19-119092390082-8. M.: FIC IU RAN, 2020. 117 s. (in Russian).
13. Patent № 2601145 (RF) Programmiruemoe logicheskoe ustrojstvo. S.F. Tyurin, A.N. Kamenskih, A.Yu. Plotnikova. 2016 (in Russian).
14. Patent №2805759 (RF). Programmiruemoe logicheskoe ustrojstvo. S.F. Tyurin, A.Yu. Skornyakova, Yu.A. Stepchenkov, Yu.G. D'yachenko, M.S. Nikitin. 2023 (in Russian).
15. Ivanova K.M., Tyurin S.F., Chikarenko S.K. Logicheskij element FPGA, konfiguriruemyj na samosinhronnyj ili sinhronnyj rezhim. V sb.: Avtomatizirovannye sistemy upravleniya i informacionnye tekhnologii. Materialy vseros. nauch.-tekhn. konf.: V 2 t. Perm'. 2021. S. 185–191 (in Russian).
16. Mehta N., An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture using Component-Specific Mapping, Ph.D. Thesis, California Institute of Technology [Online]. URL: http://thesis.library.caltech.edu/7226/1/Nikil-Mehta-2013.pdf (accessed 19.06.2024).
17. Sajt razrabotchika National Instruments. [Elektronnyj resurs]. URL: http://www.ni.com/multisim/ (data obrashcheniya: 19.06.2024).
18. Microwind & Dsch Version 3.5. [Elektronnyj resurs]. URL: http://auto.teipir.gr/sites/default/files/microwind_manual_lite_v35.pdf (data obrashcheniya: 19.06.2024).