A.A. Zatsarinny1, Yu.A. Stepchenkov2, Yu.G. Diachenko3, N.V. Morozov4, D.Yu. Stepchenkov5

1–5 FRC CSC RAS (Moscow, Russia)
1 AZatsarinny@frscsc.ru, 2 YStepchenkov@ipiran.ru, 3 diaura@mail.ru, 4 NMorozov@ipiran.ru, 5 stepchenkov@mail.ru

Over the past sixty years, self-timed (ST) digital circuits have been developed as an alternative to synchronous counterparts, operating on the principles of cause-and-effect relationships between interacting digital units. Due to hardware redundancy and two-phase work discipline with mandatory indication of successful completion of switching to the next phase, they have a number of advantages compared to synchronous counterparts. ST circuits are characterized by a much wider range of operability in terms of supply voltage and ambient temperature and function reliably at any logic cell delays determined by the current operating conditions. Due to their properties, ST circuits guarantee the detection and localization of any stuck faults. Moreover, they are characterized by a higher level of protection against soft errors and failures. Therefore, they are a promising circuit design basis for the development of reliable digital units operating under extreme conditions in a wide range of supply voltages. However, designing ST circuits is more labor intensive than synchronous circuits. The reason for this is hardware redundancy, the need to add an indication subcircuit and adhere to the principles of really ST circuit design. Manual development of the ST circuits does not guarantee an adequate result. In addition to probable errors and "slips" introduced into the developed circuit due to the "human factor", it may contain hidden errors due to "obvious" circuit solutions that generally do not take into account arbitrary delays in switching circuit cells. Therefore, manually designed circuits require a mandatory check for self-timing violations using analysis programs for self-timing (semi-modularity). However, at present, there are no programs for analyzing a circuit for self-timing that can correctly check a practical ST unit for belonging to the ST circuit class. The solution to the problem is an automated purposeful ST circuit synthesis, which guarantees compliance with all the operation principles of the ST circuits and therefore does not require checking the result for self-timing. This article describes the route of automated design of ST circuits, which complements the typical route of computer-aided design of synchronous VLSI, does not require specific knowledge of the ST circuit's theory from the user and provides the synthesis of complex digital ST circuits in full accordance with the principles of ST circuit operation and with acceptable parameters. Supplementing the standard route for automated design of synchronous digital VLSI with the stages of logical and circuit design of ST circuits allows one to combine the processes of automatic synthesis of synchronous and ST circuits in one CAD. Both synthesizes use the same initial description of the circuit operation algorithm specified in the Verilog language at any level: architectural, functional, circuitry. Heuristic methods and algorithms for converting a system of logical functions and a set of "always@" blocks into ST circuitry provide a quick and efficient way to obtain a synthesized ST solution that does not require additionally verify that the synthesized circuit belongs to the ST circuit class. In this case, methods of formalized desynchronization and substitution of ST units instead of functionally complete digital devices (adders, counters, registers, etc.) are used. The content of the standard cell library used by synchronous VLSI CAD as a design basis is extended by cells specific to ST circuits. The formalized methods and algorithms embedded in the programs for automated ST circuit synthesis free the user from routine operations that accompany the ST circuit designing process and guarantee the correct construction of a ST circuit that fulfills the features of the synthesized circuit functioning specified in the original description. The presented route of automated ST circuit synthesis and the features of the implementation of its individual stages provide a significant acceleration of the ST circuit design according to the traditional synchronous description familiar to developers of synchronous equipment, and ensure the obtaining a finished circuit that has all the advantages of ST circuits and is close to optimal consumer characteristics. This approach facilitates the use of the ST synthesizer, makes it accessible to a larger number of digital equipment developers, even for those who are only “capped” familiar with the features of ST circuit operation, and opens up broad prospects for research and implementation of ST circuitry in practice.

Zatsarinny A.A., Stepchenkov Yu.A., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu. Self-timed circuits design automation. Highly Available Systems. 2023. V. 19. № 3. P. 48−56. DOI: https://doi.org/ 10.18127/j20729472-202303-04 (in Russian)

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