S.V. Gavrilov - Dr. Sc. (Eng.), Professor, Head of Department of Digital Circuit Design Automation, Institute for design problems in microelectronics RAS (Moscow). E-mail: sergey_g @ippm.ru G.A. Ivanova - Junior Research Scientist, Department of Digital Circuit Design Automation, Institute for design problems in microelectronics RAS (Moscow). E-mail: pirutina_g@ippm.ru D.I. Ryzhova - Junior Research Scientist, Department of Digital Circuit Design Automation, Institute for design problems in microelectronics RAS (Moscow). E-mail: ryzhova_d@ippm.ru A.L. Stempkovsky - Dr. Sc. (Eng.), Academic of RAS, Professor, Director of Institute for design problems in microelectronics RAS (Moscow). E-mail: stal09@ippm.ru

With the reduction of transistors size to nanometer scale new problems, which were not solved in the existing CAD systems, are ap-peared. To improve the reliability of circuits new approaches are being developed. In some tasks, such as peak current estimation, switching interval search in the analysis of noise immunity, characterization and IP block models generation, a search of all possible switching intervals is required. Particularly, in the noise analysis estimation, the time interval intersection for aggressor and victim nodes switching is calculated. For IR-drop estimation, the analysis of simultaneous switching of large gate sets is required. In this paper the method of IP blocks performance analysis is provided. It increases the accuracy of the delay intervals analysis at the logical level in comparison with the classical methods of static timing analysis by sharing propagation of delay intervals and Boolean information about vectors of switching for which the delay is achievable.

 

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