I.V. Zhukova – Undergraduate, Department «Computer systems and networks», Kaluga branch of the Bauman MSTU E-mail: zhukova.irina93@gmail.com

A.V. Rodionov – Ph.D.(Eng.), Associate Professor, Department «Computer systems and networks»,  Kaluga branch of the Bauman MSTU

E-mail: andviro@gmail.com

I.V. Chukhraev – Ph.D.(Eng.), Associate Professor, Head of Department «Computer systems and networks»,  Kaluga branch of the Bauman MSTU

E-mail: chukhraev@bmstu-kaluga.ru

Problems of the ensuring the efficiency of the development testing of systems on a chip in conditions of replacing the imported element base with the domestic one are considered. The shortcomings of systems with foreign components are revealed, their domestic analogues, which allow to solve the problem of reducing the cost of a microassembly due to the absence of hulls of its elements, are descibed. The features of testing microassemblies on the example of the unit of the speech-forming device, which is part of the communication system, are considered. A technique for virtual testing of a system on a chip is proposed, with the project divided into modules. The results of testing of individual microassembly modules are described.

1. Tarasov I.E., Pevczov E.F. Programmiruemy’e logicheskie sxemy’ i ix primenenie v sxemotexnicheskix resheniyax. M.: MGTU MIRE’A. 2012.
2. Polovinkin A.I. Osnovy’ inzhenernogo tvorchestva: Ucheb. posobie dlya studentov vtuzov. M.: Mashinostroenie. 1988. 368 s.
3. Zhukova I.V., Rodionov A.V. Obzor metodov testirovaniya mikroproczessorov // Materialy’ Vseros. nauchno-texnich. konf. 15−17 noyabrya 2016. g. Kaluga: Izd-vo MGTU im. N.E’. Baumana. 2016. T. 4. 204 s.
4. Mosin S.G. Podxod k vy’boru metoda testirovaniya slozhny’x integral’ny’x sxem na osnove stoimostnoj modeli // Sb. trudov «Upravlenie bol’shimi sistemami». 2013. № 41. S. 344−355.
5. Tarasov I.E. Razrabotka czifrovy’x ustrojstv na osnove PLIS Xilinx s primeneniem yazy’ka VHDL. M.: Goryachaya liniya – Telekom. 2005.
6. Zhukova I.V., Rodionov A.V. Razrabotka sistemy’ testovogo okruzheniya i modelirovaniya mikrosborki s ispol’zovaniem oblachnoj texnologii na osnove REST-servisa // Mezhdunar. nauchny’j zhurnal «Innovaczionnaya nauka» (Ufa: NICz «Ae’terna»). 2017. № 7. S. 9−12.
7. Seung Eun Lee. Reusing existing resourses for testing a multi-processor system-on-chip // International Journal of Electronics. 2013. V. 100. № 3.
8. Luiza de Macedo Mourelle, Nadia Nedjah, Fabio Goncalves Pessanha. Multiprocessor system-on-chip with shared memory using crossbar topology // International Journal of Electronics. 2015. V. 102. № 1.
9. Chi-Chou Kao. Interface circuit synthesis of system-on-chip // International Journal of Electronics.