350 rub
Journal Electromagnetic Waves and Electronic Systems №11 for 2011 г.
Article in number:
Minimizing Short Channel Effects to Performance of Double Gate-Underlap Design SOI CMOS Nanotransistors
Keywords: double gate SOI nanotransistor logic gate low supply power
Authors:
N.V. Masalsky
Abstract:
The double gate short ? channel SOI («silicon on isolator») transistors with thin working area are considered as one of the most perspective directions of development of low-power and highly effective applications. One of perspective architecture of the transistor is the concept «without overlapping» a gate-drain/source of the extended areas. It is based on an optimum choice of a concentration doping gradient of the extended areas of a drain/source and a longitudinal spacer between a drain/source and gate. Suppression of short ? channel effects in such transistors is achieved by a corresponding choice of topological and technological parameters. Criteria of a choice of technological parameters for minimization of short - channel effects are considered. The best compromise for the decision of the given problem is modulation of length of the channel which is carried out with the help as variations of a drain ? source doping gradient, and a gate-drain/source spacer. Thus of value of oxide film thickness of front and back gates and thickness of working area should be fixed. By means of program HSPICE dynamic characteristics of gates the inverter, NAND2, NOR2 are numerically investigated at a supply voltage 1 V on the chosen type of transistors with channel length 22 nanometers for high-speed applications and applications with a low level of static power. Values of front oxide film thickness and thickness of working area are chosen so that quantum effects did not influence work of transistors. From results of modelling follows, that the maximal gates delay time is less 5 ps, the maximal switching active power of on frequency 100 GHz does not exceed 30 mkW. The minimal static power is equal 1.1 pW. The opportunity for creation of low-power circuitry in 100 GHz a range is shown.
Pages: 41-47
References
  1. International technology roadmap for semiconductor 2006 edition. Available from: (http://public.itrs.net).
  2. Luyken R.J., Schultz T., Hartwich J., Dreeskornfeld L., Stadele M., and Risch L. Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime // Solid-State Electronics. 2003. V. 47. P. 1199-1203.
  3. Kawamoto A., Sato S., Omura Y. Engineering S/D diffusion for sub-100-nm channel SOIMOSFETs // IEEE Trans Electron Devices. 2004. V. 51. P. 907-913.
  4. Shenoy R.S., Saraswat K.C.Optimisation of extrinsic source/drain resistance in ultrathin body double-gate FETs // IEEE Trans Nanotechnology. 2003. V. 2. P. 265-270.
  5. Lim T.C., Armstrong G.A. Parameter sensitivity for Optimal design of 65 nm node double gate SOI transistors // Solid-State Electronics. 2005. V. 49. P. 1034-1043.
  6. Kranti A., Armstrong G.A.Performance assessment of nanoscale double and triple gate FinFETs. // Semiconductor Science and Technology. 2006. V. 21. P. 409-421.
  7. Kranti A., Armstrong G.A.Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations // Solid - State Electronics. 2006. V. 50. P. 437 - 447.
  8. Kranti A. and Armstrong G.A.Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-кgate dielectrics // Semiconductor Science and Technology. 2006. V. 21. P. 1563-1572.
  9. Colinge J.-P. Silicon on Insulator Technology: Materials to VLSI. Kluver Acad. Publ. Boston. Dordrecht. London. 1997.
  10. Liang X., Taur Y.A 2-D Analytical Solution for SCEs in DG MOSFETs // IEEE Trans Electron Devices. 2004. V. 51. P. 1385-1391.
  11. Kranti A., Hao Y., Armstrong G.A.Performance projections and design optimizationof planar double gate SOI MOSFETs for logic technology applications // Semiconductor Science and Technology. 2008. V. 23.
  12. Kathawala G A, Winstead B, Ravaioli U. Monte Carlo simulations of double-gate MOSFETs // IEEE Trans. ElectronDevices. 2003. V. 50. P. 2467-73.
  13. Orlikovsky A., Vyurkov V., Lukichev V., Semenikhin I., Khomyakov A. All quantum simulation of ultrathin SOI MOSFET. NATO Security Through ScienceSeries-Nanoscaled Semiconductor-on-Insulator Structuresand Devices(Berlin: Springer). 2007. P. 323-40.
  14. Gilbert M. J., Ferry D. K. Vorticity and quantum interference in ultra-small SOI MOSFETs // IEEE Trans.Nanotechnol. 2005. V. 4. P. 355-9.
  15. Taur Y.Analytical solutions of charge and capacitance in symmetric double date MOSFETs // IEEE Trans. Electron Devices.2001.V. 48. P. 2861-9.
  16. Kranti A., Armstrong G.A.Design and optimization of FinFETs for ultra-low-voltage analog applications // IEEE Trans. Electron Devices. 2007. V. 54. № 12. P. 3308-3316.
  17. Захаров С.М., Масальский Н.В., Шафигуллин М.М. Проблемы схемотехнического моделирования интегральных схем // Успехи современной радиоэлектроники. 2005. № 2. С. 43-50.
  18. ATLAS Users Manual, SILVACO. 2006.
  19. Kranti A., Armstrong G. A.Insights into gate-underlap design in FinFETs for ultra-low voltage analog performance // IEEE SOI Conf. 2007. P. 33-4.
  20. Uchida K., Koga J., Takagi S. Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs-coulomb scattering, volume inversion and δTSOI-induced scattering // Proc. IEDM Tech.Dig. 2003. P. 805-8.