A.B. Pun – Post-graduate Student, Moscow Institute of Physics and Technology
E-mail: pun.ab@mipt.ru
D.A. Gavrilov – Ph.D. (Eng.), Associate Professor, Head of Laboratory, Moscow Institute of Physics and Technology E-mail: gavrilov.da@mipt.ru
N.N. Shchelkunov – Ph.D. (Eng.), Vice-chairman of Radioelectronics and Applied Informatics Chair, Moscow Institute of Physics and Technology
E-mail: shchelkunov.nn@mipt.ru
A.A. Fortunatov – Ph.D. (Phys.-Math.), Assistent, Moscow Institute of Physics and Technology E-mail: fortunatov.aa@mipt.ru
In the paper we present a description of the hardware accelerator implementation of the adaptive binarization algorithm on a programmable logic device. General description of the binarization algorithm and the principle of operation of the adaptive binarization algorithm are given. The proposed algorithm has a multiscale for the selection objects of different sizes. The description of the main modules is presented. The required resources for the described implementation have been identified.
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