A.S. Pravitel - Design Engineer, JSC Academician M.F. Reshetnev ISS (Zheleznogorsk) E-mail: pravitel@iss-reshetnev.ru

The memory modules are part of the highly reliable electronics, designed for modern spacecraft are subjected to the combined effect of destabilizing factors of the outer space. There are many destabilizing factors that affects to the data stored in the memory modules (internal or external) but the ionizing radiation brings the largest negative effect. A high level of reliability and stability of very large scale integrated circuits is achieved by using a range of measures at all stages of planning and preparation, for example, technology design, circuit design and design solutions. The most common way to solve the problem of increasing the fault tolerance is the double or triple mode redundancy. The error detection and correction technique is the main memory protection method. Depending on the type of error correction code it is possible to detect and correct various number of errors (single or double adjacent, etc). Error correction codes are characterized by various degrees of redundancy check bits and the time delays for verifying and corrective actions. In high-reliability electronic control systems based on digital element base with low degree of integration, most approaches may not provide an adequate level of weight and size, energy consumption and delays of the electronic equipment. Moreover, single error cor-rection and double error detection may not provide adequate protection against memory faults. An urgent task is the use of multiple-error correction codes. Although many powerful error control methods (including Reed-Solomon) are capable of correcting multiple bytes of error, the general drawback with these methods is latency and speed. Most of these codes require at least several cycles to complete the first correction. Increasing complexity and growing demands to unify electronics cause the development of new methods for the design and architectural organization of IP cores that provide the work with memory modules. It is required to research and to evaluate different methods of error correcting codes by the following criteria: 1. The complexity of implementation in the digital integrated circuits (the number of the occupied area on the chip and power con-sumption). 2. Decoding procedure should have a low computational complexity and latency. 3. The minimum number of redundant symbols with a required level of correcting ability. As a result of research it has been implemented three IP blocks based on the error correction codes that allow correcting single or multiple errors. IP-cores have been compared according to the criteria given above. In the next stage of research it is necessary to modify Reed-Muller code that allow reducing hardware costs, delay and improve the decoding operation. Also need to consider other promising code design, for example, codes with a low density parity check, polar codes and concatenated codes.

 

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