V.A. Goryachev

On the basis of simple models for different line communications (LC) of silicon VLSI (type GSI system on a crystal) physical characteristics interconnection of low-power silicon CMOS elements of high-speed microprocessors are considered. For the purpose of optimization circuit design the microprocessor questions of operation LС with planar topology, elements of 3-dimensional connections and synchronization are discussed. Strip, unbalanced lines with interlay transitions to RC and RLC models; the symmetric, differential LС and screened connections are analyzed. The width of conductors nanotransistors integrated circuits (IС) is comparable to their thickness and makes units of microns and less is shown. The topological features of a LС define maximum permissible lengths of lines, but restrictions on length of electrical communications on admissible current density, appear more "rigid" when lowering the technological sizes, than the restrictions caused by required time of switching is marked. The resistance of copper conductors is defined by a microstructure of a blanket and essentially depends on metallization technology is shown. In standard cases when losses in lines are spent for heating of conductors, surface resistance of metal characterizes power efficiency of interconnecting. Now frequencies of digital pulses grew to tens Gigahertz and a specific type transverse section of conductors, features of their conductivities and topology make essential impact on transmission characteristics of signals. Thus, reserves of energy saving and increase in productivity of separate units can be found at different development stages and VLSI enhancements. However development of timing circuits low-power SOI CMOS microprocessors in systems on a crystal has not single-digit perspective. For the solution of this problem it is possible to use carbonic high-conductivity materials instead of copper and, moreover, optical connections. Besides, in department of microelectronic technology military aerospace USA (DARPA) placement on one silicon crystal of electronic and optical systems of the mixed signal processing is declared preparation of the program (E-PH1) on the Heterogeneous Integration, allowing. The technologies developed within this program shall provide the considerable improving of characteristics microprocessors and reduction of their sizes in comparison with existing technologies. Thus, in development of element basis high speed electronics the significant progress caused by mastering of technology nanometer level in metal-dielectric quality structures is planned.