Research of the methods of the form used representation of the topology and microarchitecture of integrates microchips
- 1 д.т.н., доцент, Военно-космическая академия имени А.Ф. Можайского (Санкт-Петербург)
- 2 д.т.н., доцент, Череповецкое высшее военное инженерное училище радиоэлектроники
- 3 адъюнкт, Военно-космическая академия имени А.Ф. Можайского (Санкт-Петербург) Д.А Хапилина – инженер, Военно-космическая академия имени А.Ф. Можайского (Санкт-Петербург)
Abstract
The existing dependence of critical systems and critical types of equipment on electronic means (including LSI and VLSI) produced at factories that cannot be fully relied upon, necessitates the development of a new area of research – reverse engineering in microelectronics. In the interests of reproducing the functional analogue of a technical system by analyzing it and using additional available information about its structure and functions, it is advisable to study approaches to a formalized representation of the topology and microarchitecture of integrated circuits.
Purpose of the work is to study methods of formalized presentation of the topology and microarchitecture of integrated circuits in the interest of reproducing a functional analog of a technical system by analyzing it and using additional available information about its structure and functions.
The basic methods of a formalized representation of the topology and microarchitecture of large integrated circuits and ultra-large integrated circuits are considered. Examples are given that show that it is advisable to use HDL SystemVerilog and VHDL to automate the process steps of reverse engineering. When designing LSI and VLSI, it is preferable to use SystemVerilοg.
The descriptions presented allow us to systematize the data obtained after the studies, which can help speed up the process of individual design stages and, accordingly, dynamize the complete reverse engineering process.
How to cite
Сазонов К.В., Тавалинский Д.А., Абашева И.В. Исследование методов формализованного представления топологии и микроархитектуры интегральных микросхем // Информационно-измерительные и управляющие системы. 2020. № 3. С. 69–76. DOI: https://doi.org/10.18127/j20700814-202003-08
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