Features of State Machine File synthesis process using Altera Quartus II

The process of finite state machine synthesis in Quartus II, using a State Machine Editor feature, is reviewed. It is shown that, during the automatic synthesis, firmware control device is built using the unitary code for encoding the states of a state machine. Altera FPGA-s Logic Cell Comb settings of the LUT elements were explained. Features of the resulting circuit were studied with the aid of Altera Map Viewer. Features of the states encoding process within the process of automating synthesis of a finite state machine (firmware control device in Quartus II system) were analyzed with the aid of State Machine Editor and VHDL. It is shown, that, by default, in auto-synthesis mode, unitary code (One-hot encoding) is used. State Machine Editor settings were studied, and alternate possible encoding mode (Minimal Bits Encoding) is set. Logic functions, implemented by LUT, were analyzed, and main features of an obtained state machine were estimated using the Map Viewer tool.