D.M. Afanasyev1, I.B. Pugachev2
1 Russian State Social University (Moscow, Russia)
2 MIREA – Russian Technological University (Moscow, Russia)
The problem of distinguishing the operation of stack-based, register-based, and accumulator-based processors is considered. A textual and practical implementation of program-code execution on these types of processor architectures is presented. From the standpoint of register operation in an accumulator architecture, it can be argued that this architecture is a special case of register-based processors, considering the system logic of using registers as assignable variables. It is shown that the register-based architecture has a more complex software implementation in a low-level programming language.
Problem Statement. When working with assembly code across different types of software implementations of processor architectures, it is necessary to focus on the way it addresses permanent memory. Due to a lack of knowledge about the key features and differences of processor architectures, most information technology specialists may not understand the specific characteristics of processor operation and may make errors when working with them. As of today, there is no generally accepted methodology for working with regard to the differences among existing processor architectures: stack-based, accumulator-based, and register-based. Existing works provide an understanding of the operation of a register-based processor but do not fully solve the educational and research problems encountered in practice that are associated with stack-based processors [1–5].
Objective. To formulate systemic factors that consider the specificity of different types of processor architectures, considering significant differences in instruction processing by using the logic of computation with arithmetic operations as an example.
Results. An analysis of the subject area was carried out, and the principal differences between stack-based and register-based processors were established. An analogy for classifying the accumulator-based processor as a special case of the register-based architecture is proposed and substantiated. A conclusion is drawn regarding the size of assembly code in the software implementation of register-based and stack-based processor architectures.
Practical Significance. The presented results may be used in the development of educational laboratory stands and virtual simulators for teaching digital circuit design based on the architectures under consideration, in the creation of experimental tools for static and dynamic translation of program code, as well as in the preparation of methodological materials for porting low-level software.
Afanasyev D.M., Pugachev I.B. On the principal significant differences between stack-based and register-based processors // Achievements of modern radioelectronics. 2026. V. 80. № 7. P. 40–45. DOI: https://doi.org/10.18127/j20700784-202607-04
- Krejgon X. Arxitektura komp`yuterov i eyo realizaciya. Per. s angl. M.: Mir. 2004. 416 s. (in Russian).
- Intel Corporation. Intel 80386 Programmers Reference Manual [E`lektronny`j resurs]. URL: https://css.csail.mit.edu/6.858/2014/readings/i386.pdf (data obrashheniya: 19.10.2025).
- Pugachyov I.B., Afanas`ev D.M. Yazy`ki programmirovaniya nizkogo urovnya: Praktikum: uchebnoe posobie. M.: RTU MIRE`A. 2025. 79 s. (in Russian).
- Quynh N.A. Capstone: Next-Gen Disassembly Framework. Black Hat USA, 2014 [E`lektronny`j resurs]. URL: https://www.capstone-engine.org/BHUSA2014-capstone.pdf (data obrashheniya: 01.02.2026).
- Nethercote N., Seward J. Valgrind: A Framework for Heavyweight Dynamic Binary Instrumentation. Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation. 2007. P. 89–100.
- Grodzenskij S.Ya., Emanakov I.V., Ovchinnikov S.A. Metodika vy`yavleniya poter` v proizvodstvennoj sisteme. Naukoemkie texnologii. 2018. № 1. S. 10–13. (in Russian).
- Grodzenskij S.Ya., Grodzenskij Ya.S. Metod Pareto: istoriya, novy`e vozmozhnosti, perspektivy`. Nelinejny`j mir. 2023. № 1. S. 47–53. DOI: https://doi.org/10.18127/j20700970-202301-06 (in Russian).
- Grodzenskij S.Ya., Kalacheva E.A. Informacionny`e texnologii: istoriya razvitiya i stanovleniya. Nelinejny`j mir. 2016. № 5. S. 74–79. (in Russian).
- Grodzenskij S.Ya., Chesalin A.N. Ispol`zovanie apparata nechetkoj logiki dlya ocenki nadezhnosti avtomatizirovanny`x system. Nelinejny`j mir. 2017. № 4. S. 17–24. (in Russian).
- Grodzenskij S.Ya., Chesalin A.N., Ovchinnikov S.A., Nilov M.Yu., Fam Van Ty`. Strategiya razvitiya produkcii na osnove sinteza strukturirovaniya funkcii kachestva i faktornogo e`ksperimenta. Uspexi sovremennoj radioe`lektroniki. 2019. № 7. S. 37–44. DOI: 10.18127/j20700784-201907-05 (in Russian).
- Borzov D.B., Tipikin A.P. Proektirovanie processora E`VM: Uchebnoe posobie. Kursk: Kursk. gos. texn. un-t. 2006. 185 s. (in Russian).

