Features of the manufacturing process for power ICs with submicron design standards

The generally accepted method for manufacturing power ICs is BCD. The key element in BCD technology is the double-diffused MOSFET. Integrating the double-diffused MOSFET into the submicron SOI CMOS process is a pressing challenge in the development of BCD technology. Solving the problem of integrating the double-diffused MOSFET will expand the product range with minimal costs while maintaining the key advantages of mass-produced submicron SOI CMOS ICs. The goal was to develop a manufacturing process for n- and p-channel LDMOS transistors based on the basic 0.35 µm SOI CMOS process with a 200 nm device layer thickness and a 200 nm buried oxide thickness. The result was a process for producing high-voltage double-diffused MOSFET transistors. The technological features of high-voltage MOSFET transistors based on a SOI structure are discussed. The operating mode of these high-voltage MOSFETs is an operating drain voltage of 12 V and an off-state breakdown voltage of over 30 V. The feasibility of manufacturing such transistors is experimentally confirmed. High-voltage transistors manufactured using a 0.35 µm SOI CMOS process are studied. The optimal geometric parameters of the key regions are determined. The developed process enables the production of low-voltage integrated circuits with a supply voltage of 3.3 V and power integrated circuits with a supply voltage of up to 12 V. A BCD process based on the solutions applied in this work will be developed in the future.