Massively-parallel processing architecture of - system-on-chip - class devices for high-performance statistical processing in measurement and control systems

The development of microelectronic-s element base and the growth of the level of component integration on a chip gives an opportunity to produce devices of mass-parallel architecture. At the same time the high preproduction cost demands the search of computing tasks claimed at different application spheres, providing thereby appropriate amount consumed of the component base being developed. The article deals with a variety of a multiscale analysis based on the parallel computing of a posteriori probability according to Bayes theorem used for statistical processing of measurements in digital measure and control systems. Applicability of mass-parallel algorithms for the given computing task allowed realization the prototype of this hardware platform using effectively the possibilities of a microelecronic component base with high level of component integration. The memory bandwidth achieved and overall performance for the prototype made on the base of high-efficiency PLD with FPGA architecture exceeded essentially the analog characteristics of the universal computing architectures such as general-purpose computers and distributed computer systems on the base of GPU.