Article or book title, author's surname, DOI

D.Yu. Diachenko

Д.Ю. Дьяченко

2 articles 2023–2025

2025

  1. Self-timed shift register implementation according to synchronous counterpart Verilog-description Highly available systems, No. 3, 2025 pp. 58-68

2023

  1. Self-timed pipeline optimization Highly available systems, No. 1, 2023 pp. 5-13