A.A. Pavlov1, A.N. Tsarkov2, Yu.А. Romanenko3, O.F. Pashaev4, A.Yu. Romanenko5, F.A. Pavlov6

1,3,4,6  Military Academy of the Strategic Missile Forces n.a. Peter the Great (branch in Serpukhov) (Serpukhov, Russia)

2,5 Autonomous Non-Profit Organization “Institute of Engineering Physics” (ANO “IIF”) (Serpukhov, Russia)

1,6 Pavlov_iif@mail.ru; 2 info@iifrf.ru

The development of modern digital data transmission systems (DDTS), which include specialized computers (SEVM), is associated with solving the problem of ensuring high values of the indicators characterizing their operation: the probability of failure-free operation, survivability, self-healing ability and speed. For this purpose, various backup methods are used to ensure the restoration of the operability of the functional devices of the SEVM [6,7,8,9].

The Hamming code is most widely used to correct single errors. At the same time, the disadvantage of using the Hamming code is the lack of control over the logical inversion operation.

In addition, there is a need to correct errors of greater multiplicity. The aim of the work is to develop a correction code with increased correction capacity that controls the logical operation of inversion without additional time costs.

Results. The developed algebraic code allows correcting errors in direct and inverse values of the code set when performing arithmetic and logical operations of the processor.

The rules for grouping error syndrome bits into bits are formulated that determine:

a block of information bits containing an error;

an erroneous bit in a 3-bit information block.

The properties of the algebraic code that ensure the possibility of correcting:

single errors in information bits;

multiple errors in check bits;

A decoding algorithm has been developed that forms the values ​​of the error syndrome bits:

determining the address of the information block containing the error and the number of the erroneous bit in a three-bit information block;

ensuring the correction of multiple errors in check bits.

The practical significance lies in the fact that the developed algebraic linear code with increased correcting capacity allows:

to control the logical operation of inversion without changing the values ​​of the check bits and additional time costs;

ensures the correction of single errors and double errors in two junior check bits (determining the number of the erroneous bit in a three-bit information block);

ensures the correction of errors of arbitrary multiplicity in senior check bits (determining the number of the information block containing the error).

Pavlov A.A., Tsarkov A.N., Romanenko Yu.А., Pashaev O.F., Romanenko A.Yu., Pavlov F.A. Using the properties of an algebraic code to improve the efficiency of detecting and correcting errors in information storage and processing devices. Radiotekhnika. 2025.
V. 89. № 4. P. 101−108. DOI: https://doi.org/10.18127/j00338486-202504-08 (In Russian)

1. Grebeshkov A.Ju. Mikroprocessornye sistemy i programmnoe obespechenie v sredstvah svjazi. Samara: PGUTI. 2009. 298 s. (in Russian).
2. GOST 27.003-2016. Nadezhnost' v tehnike. Sostav i obshhie pravila zadanija trebovanij po nadezhnosti. M: FGUP «Standartinform». 2018. 19 s. (in Russian).
3. GOST 27.102-202.1 Nadezhnost' v tehnike. Nadezhnost' ob’ekta. Terminy i opredelenija.  M: FGUP «Standartinform». 2022. 46 s. (in Russian).
4. Pavlov A.A., Car'kov A.N., Romanenko Ju.A., Korneev I.I., Romanenko A.Ju., Makeev M.I., Pavlov F.A. Obnaruzhenie i korrekcija oshibok v ustrojstvah obrabotki informacii v sistemah svjazi i telekommunikacii. Radiotehnika. 2023. T. 87. № 3. S. 6-14. DOI: https://doi.org/10.18127/j00338486-202303-14 (in Russian).
5. Pavlov A.A., Car'kov A.N., Romanenko Ju.A., Pashincev V.P., Romanenko A.Ju., Makeev M.I., Pavlov F.A. Ispol'zovanie informacionnogo rezervirovanija dlja povyshenija nadezhnosti ustrojstv hranenija, obrabotki i peredachi informacii. Radiotehnika. 2024. T. 88.
   № 2. S. 168−176. DOI: https://doi.org/10.18127/j00338486-202402-16 (in Russian).
6. Shherbakov N.S. Dostovernost' raboty cifrovyh ustrojstv. M.: Mashinostroenie. 1989. 224 s. (in Russian).
7. Naseer R., Draper J. Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs. Information Sciences Institute University of Southern California. IEEE Trans Device. Mater. 2008. V. 6. P. 222-225.
8. Prager K., Vahey M., Farwell W., Whitney J., Lieb J. A fault tolerant signal processing computer. Dependable Systems and Networks, 2000. DSN 2000. Proceedings International Conference on. 2000. P. 169-174.
9. Micheloni R., Marelli A., Ravasio R. Error correction codes for non-volatile memories. Breinigsville: Springer. 2010. 337 p.
10. Todd K.M. Error correction coding. Mathematical methods and algorithms. New Jersey: Wiley. 2005.