350 rub
Journal Radioengineering №2 for 2024 г.
Article in number:
Use of information redundancy to increase the reliability of devices for storing, processing and transmitting information
Type of article: scientific article
DOI: https://doi.org/10.18127/j00338486-202402-16
UDC: 004.052.2
Authors:

A.A. Pavlov1, A.N. Tsarkov2, Yu.А. Romanenko3, V.P. Pashintsev4, A.Yu. Romanenko5, M.I. Makeev6, F.A. Pavlov7

1,3,5-7 Military Academy of the Strategic Missile Forces n.a. Peter the Great (branch in Serpukhov) (Serpukhov, Russia)

2 Autonomous non-profit organization "Institute of Engineering Physics" (ANO "IIF") (Serpukhov, Russia)

4 North Caucasus Federal University, Institute of Digital Development (Stavrapol, Russia)

1 Pavlov_iif@mail.ru; 2,3,5,6 info@iifrf.ru; 4 pashintsevp@mail.ru; 7 Pavlov_iif@mail.ru

Abstract:

In modern information transmission systems, a special place is occupied by telecommunication systems (TS), which include digital data transmission systems (DSTS) containing specialized computers (SEVMs).

The systems under consideration must ensure fast and reliable transmission of discrete data over communication lines. In this case, the loss of even one transmitted character is unacceptable; therefore, the main indicator of the reliability of a computer is the probability of failure-free operation.

To increase the probability of failure-free operation of a storage device (MS), corrective codes and duplication are used, and to increase the probability of failure-free operation of the arithmetic-logical unit (ALU) of a computer, majority redundancy is used.

The disadvantage of the majority method is the high hardware costs for redundancy, which reduces the efficiency of its use.

The disadvantages of using correction codes include:

as a rule, they are used for separate redundancy (detection and correction of errors that occur in storage devices; majority redundancy is used to detect and correct errors in the ALU);

not all arithmetic and logical operations can be controlled based on existing correcting codes;

a sharp increase in hardware costs when using algebraic linear codes to detect and correct multiple errors.

Detection of errors in the ALU of a computer processor can be achieved on the basis of duplication in a loaded mode with replacement, however, this is associated with solving the main problem of computer duplication: - selection of monitoring tools for determining a failed channel (detection of errors in storage and information processing devices).

The purpose of the research is to develop a scientific and methodological apparatus for computer backup using the duplication method with error detection in backup channels based on the use of an algebraic linear code, which makes it possible to detect errors not only in storage devices, but also adapted for detecting errors when performing arithmetic and logical operations.

Results. An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of telecommunication systems was carried out.

Requirements for computer backup methods are formulated.

A comparative assessment of the detecting ability and hardware costs was carried out when implementing the majority redundancy method, the duplication method and the use of correcting codes.

The expediency of using the duplication method is substantiated to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes to determine the faulty channel, which allows to significantly reduce hardware costs for constructing monitoring equipment and use 10-30% of backup equipment for these purposes.

It is proposed to use an algebraic linear code, in which, unlike well-known codes, the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical inversion operation , necessary to represent a negative number in two's complement code, which makes it possible to adapt the code to control arithmetic and logical operations of the computer processor.

An assessment was made of the probability of failure-free operation of a duplicated computer, with its general redundancy, with detection and correction of single errors in the backup memory channels and detection of errors in the backup channels of the processor ALU based on the proposed code, and an assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method.

A comparative assessment of the probabilities of failure-free operation allows us to conclude that the general redundancy of the computer based on the proposed code, in comparison with the separate redundancy of the memory and ALU of the computer processor, allows for a gain in the probability of failure-free operation of the computer and its functional devices throughout the entire period of operation.

The practical significance lies in the fact that the proposed scientific and methodological apparatus provides:

reduction of hardware costs for identifying a faulty channel when organizing duplication;

detection of errors in the memory and ALU of the computer processor with time costs not exceeding the time of error detection when using standard methods of monitoring the computer system.

Pages: 127-137
For citation

Pavlov A.A., Tsarkov A.N., Romanenko Yu.А., Pashintsev V.P., Romanenko A.Yu., Makeev M.I., Pavlov F.A. Use of information re-dundancy to increase the reliability of devices for storing, processing and transmitting information. Radiotekhnika. 2024. V. 88. № 2. P. 127−137. DOI: https://doi.org/10.18127/j00338486-202402-16 (In Russian)

References
  1. GOST 27.003-2016. Nadezhnost' v tehnike. Sostav i obshhie pravila zadanija trebovanij po nadezhnosti. M: FGUP «STAN-DARTINFORM», 2018. 19 s. (in Russian).
  2. GOST 27.102-2021 Nadezhnost' v tehnike. Nadezhnost' ob#ekta. Terminy i opredelenija. M: FGUP «STANDART-INFORM», 2022. 46 s.
  3. Pavlov A.A., Car'kov A.N., Korneev I.I., Romanenko A.Ju., Makeev M.I., Pavlov F.A. Metodicheskij apparat zashhity ot oshibok processorov specializirovannyh JeVM. Vestnik komp'juternyh i informacionnyh tehnologij. 2023. № 3. S. 3-8 (in Russian).
  4. Pavlov A.A., Pavlov Al.A., Pavlov A.P., Car'kov A.N., Horuzhenko O.V. Kontrol' processora v avtomatizirovannyh izmeritel'nyh sistemah. Izmeritel'naja tehnika. 2011. № 2. S. 12-15 (in Russian).
  5. Pavlov A.A., Pavlov Al.A., Pavlov P.A., Car'kov A.N., Horuzhenko O.V. Metod kontrolja ALU pri vypolnenii arifmeti-cheskih i logicheskih operacij. Kontrol'. Diagnostika. 2011. № 3(153). S. 48-54 (in Russian).
  6. Presnuhin L.N., Nesterov P.V. Cifrovye vychislitel'nye mashiny. M: Vysshaja shkola. 1981. 511 s. (in Russian).
  7. Shherbakov N.S. Samokorrektirujushhiesja diskretnye ustrojstva. M.: Mashinostroenie, 1975. 214 s. (in Russian).
  8. Shherbakov N.S. Dostovernost' raboty cifrovyh ustrojstv. M.: Mashinostroenie. 1989. 224 s. (in Russian). 
  9. Naseer R., Draper J. Parallel Double Error Correcting Code Design to Mitigate Multi-Bit Upsets in SRAMs. Information Sciences Institute University of Southern California, IEEE Trans Device. Mater 2008. V. 6. P. 222-225.
  10. Prager K., Vahey M., Farwell W., Whitney J., Lieb J. A fault tolerant signal processing computer. Dependable Systems and Networks, 2000. DSN 2000. Proceedings International Conference on. 2000. P. 169-174.
  11. Pavlov A.A., Tsarkov A.N., Romanenko Yu.A., Korneev I.I., Romanenko A.Yu., Makeev M.I., Pavlov F.A. Obnaruzhenie i korrektsiya oshibok v ustroystvakh obrabotki informatsii v sistemakh svyazi i telekommunikatsii. Radiotekhnika. 2023. Т. 87. № 3. S. 6-14. DOI: https://doi.org/10.18127/j00338486-202303-14 (in Russian).
Date of receipt: 30.11.2023
Approved after review: 05.12.2023
Accepted for publication: 29.01.2024