A.V. Bashkirov1, M.V. Horoshaylova2, P.P. Churakov3, E.V. Tureckaya4

1,2,4 Voronezh State Technical University (Voronezh, Russia)

3 Penza State University (Penza, Russia)

Formulation of the problem. Structured LDPC codes, also known as low-density quasi-cyclic parity-check codes (QC-LDPCs), have significant advantages over other types of LDPC codes in terms of hardware implementation and excellent error correction performance in noisy channels. In addition, QC-LDPC codes are relatively flexible and can be built with multiple code rates, different block lengths, and multiple different sub-array sizes, which are important features of modern mobile and wireless communication systems. The 5G standard offers a much higher level of performance compared to previous generations of mobile communication systems. Forward Error Correction (FEC) plays an extremely important role in high speed communication systems. Finding an effective trade-off between high performance, high bandwidth, low hardware complexity, low cost, and low power consumption makes hardware implementation of an LDPC decoder a challenging task. Therefore, it is extremely important to develop a high performance QC-LDPC small area FEC decoder architecture for 5G wireless communication standards.

Purpose. Analysis and development of a QC-LDPC decoder architecture focused on simplicity, high throughput and efficient use of hardware resources in accordance with 5G wireless communication specifications.

Practical significance. To implement the decoder, a combined minimum sum decoding algorithm (CMS) is used, which is a combination of the minimum offset sum algorithm and the original minimum sum algorithm. A high-performance multi-level pipeline architecture of a QC-LDPC decoder for mobile broadband access for 5G wireless standards based on the CMS algorithm with multi-level pipeline planning is presented. An effective minimum search is introduced for the architecture of the control node block, which reduces the hardware resources required to calculate the first two minima. In addition, a simplified architecture of the a posteriori information update block is presented, which requires only one array of adders to work.

Bashkirov A.V., Horoshaylova M.V., Churakov P.P., Tureckaya E.V. Development of QC-LDPC-decoder with high capacity for 5G wireless radio. Radiotekhnika. 2022. V. 86. № 7. P. 14−19. DOI: https://doi.org/10.18127/j00338486-202207-03 (In Russian)

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