A.A. Sukhanov1, I.A. Grigoryev2

1,2 PJSC «Radiofizika» (Moscow, Russia)

1 MIPT (National Research University) (Moscow)

1 aleksandr.sukhanov@phystech.edu; 2 iv.grigoryev@gmail.com

Problem statement. Developed synthesizers must meet the requirements for them. One of the important characteristics of the output signal of the synthesizer is the power level of the phase noise. Not only the choice of low-noise components, but also the frequency synthesis circuit affects the obtaining of minimum values. At the same time, the limitation on the level of phase noise of the output signal is often not the only requirement for the synthesizer, which forces us to solve the tasks in a complex way.

Goal. Investigate a synthesizer circuit based on a PLL loop without a divider in the feedback circuit as the most effective for constructing small-sized tunable synthesizers with low phase noise.

Results. A mathematical evaluation of phase noise in the output signal of a synthesizer based on a PLL loop without VCO frequency division, as well as other typical single-loop PLL circuits, is presented. A theoretical comparison of phase noise levels in the passband of a loop LPF is made. The results of modeling the distribution of phase noise for the synthesizer circuits under consideration are presented and compared with the direct analog synthesis method. Experimental results for some synthesizers are given.

Practical significance. The presented results can be used when choosing a frequency synthesis circuit in the development of synthesizers with a low level of phase noise, compact dimensions and a small tuning step.

Sukhanov A.A., Grigoryev I.A. Phase noise simulation of a hybrid frequency synthesizer based on a PLL LOOP without division of the VCO frequency. Radiotekhnika. 2022. V. 86. № 4. P. 22−31. DOI: https://doi.org/10.18127/j00338486-202204-03 (In Russian)

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