Yu.A. Pirogova1, S.A. Gvozdenko2, D.V. Shardakov3, O.Yu. Makarov4, A.A. Pirogov5

1−5 Voronezh State Technical University (Voronezh, Russia)

Formulation of the problem. Switching functions underlie the logic of digital devices and are widely used for the synthesis of digital circuits, since they allow you to directly obtain the architecture in the form required or available for implementation. Switching functions can be presented in two forms: perfect disjunctive normal form and perfect conjunctive normal form. It is advisable, after the synthesis of the switching function, to minimize it in such a way that it contains a minimum of variables and logical operations, which will reduce the number of gates of the digital automaton. The efficiency of the digital node depends on the minimization methods used. Debugging and verification of models based on switching functions is one of the most important tasks of the initial design stage.

Goal. Improving the efficiency of the digital device design process by reducing time costs due to the use of computer-aided design and functional verification systems at the initial design stages. Explore tools for modeling RTL circuits of digital devices, synthesizing RTL circuits in the form of standard elements of programmable logic integrated circuits (FPGAs) and their verification in the Xilinx ISE environment. Develop an optimal way of behavioral testing in the simulation mode of the iSim environment.

Results. A method for designing digital automata using tools for their description in the VHDL language is considered, which differs from construction methods using a circuit editor, in a shorter time for building an RTL model. The method includes two stages. At the first stage, the switching function of the digital node is described, the RTL model is synthesized, the truth table, the Karnaugh map, and a logical expression is constructed based on the RTL circuit in the form of standard FPGA elements. The second stage is to develop an optimal test bench for behavioral modeling of the digital automaton operation.

To achieve this goal, an arbitrary switching function of three variables given by the truth table was investigated. At the same time, the construction of a logical function was carried out using the Karnaugh map and the subsequent synthesis of the RTL circuit based on the VHDL description. The simulation results fully correspond to the original description of the function, the developed test bench allows you to form time diagrams of the digital node operation with the ability to programmatically correct the model input signals. Practical significance. The results of the work in the future can be used as ready-made test blocks for the design and verification of more complex digital devices on FPGAs. The models have an open architecture, which allows them to be adapted in the system for the required task.

Pirogova Yu.A., Gvozdenko S.A., Shardakov D.V., Makarov O.Yu., Pirogov A.A. Methods for modeling and verification of switching functions in problems of designing digital nodes. Radiotekhnika. 2021. V. 85. № 6. P. 40−46. DOI: https://doi.org/10.18127/j00338486-202106-07 (In Russian)

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