S.Yu. Beletskaya1, A.V. Bashkirov2, I.V. Sviridova3, O.V. Sviridova4

1-4 Voronezh State Technical University (Voronezh, Russia)

Formulation of the problem. Based on stochastic computations in this article, the architecture and methodical decoding. This architecture is algorithms based on factor graphs for the design of error correction decoders such as LDPC decoders and turbo decoders. There are two possible solutions to implement such decoding, such as parallel and sequential approach. In a parallel electrical circuit, processors operate simultaneously and therefore a large number of them are required. Processors are used multiple times in a single iteration and therefore requires the use of RAM to store messages. The advantages of a sequential architecture are that it requires less silicon footprint. But this approach also reduces the maximum decoder bandwidth. RAM can be limited in current FPGAs. Purpose. In this work, the goal is to obtain a simplified trust propagation algorithm. The article will compare Pearl's stochastic modeling method with the stochastic decoding algorithm. But their main difference is that the stochastic simulation method will not work for loop loops and therefore cannot be used to design error correction decoders. Also, the article will present a new stochastic decoding algorithm, in contrast to the original binary algorithm.

Results. A new stochastic algorithm for iterative decoding with error control is presented. A stochastic implementation on graphs of an acyclic code and the presented results for a stochastic decoder are described. Cyclic constraint graphs require the use of a modified node called a supernode. The results are presented for a 256-length stochastic block turbo decoder.

Practical significance. This article presents a stochastic approximation of the trust propagation algorithm. This approximation makes it possible to implement a low-complexity parallel decoder that is easy to implement on FPGAs. A simple logical node is implemented in the stochastic decoding algorithm of each processor.

Beletskaya S.Yu., Bashkirov A.V., Sviridova I.V., Sviridova O.V. Stochastic iterative decoder. Radiotekhnika. 2021. V. 85. № 6.  P. 12−16. DOI: https://doi.org/10.18127/j00338486-202106-02 (In Russian)

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