350 rub
Journal Radioengineering №3 for 2020 г.
Article in number:
Method of correction of errors in devices treatment and transfer of information
Type of article: scientific article
DOI: 10.18127/j00338486-202003(06)-02
UDC: 681.32.004.12:681.581.54
Authors:

A.A. Pavlov – Dr.Sc.(Eng.), Professor, 

Branch of Peter The Great Military Academy of Strategic Rocket Forces (Serpukhov, Moscow region) E-mail: Pavlov_iif@mail.ru

A.N. Tsarkov – Dr.Sc.(Eng.), Professor, Institute Board Chairman

Interregional Public Institution «Institute of Engineering Physics» (Serpukhov, Moscow region) E-mail: info@iifrf.ru

D.A. Korsunskiy – Research Scientist, 

Interregional Public Institution «Institute of Engineering Physics» (Serpukhov, Moscow region) E-mail: info@iifrf.ru

V.Z. Volkov – Research Scientist, 

Branch of Peter The Great Military Academy of Strategic Rocket Forces (Serpukhov, Moscow region)

V.P. Efremov – Research Scientist, 

Branch of Peter The Great Military Academy of Strategic Rocket Forces (Serpukhov, Moscow region)

Abstract:

A regular procedure is proposed for constructing a fault-tolerant computer based on the formation of a redundant channel due to the functional redundancy of the processor and the use of an algebraic linear code to control storage devices and its adaptation to control arithmetic and logical operations. The regularities are revealed that allow the use of functional devices of the processor to perform basic and duplicate functions. The calculation of hardware costs for the formation of a redundant channel and a comparative evaluation of the probability of failure-free operation from the use of the proposed reservation method has been carried out/. The use of the proposed backup method, in comparison with the majority method, allows increasing the probability of failure-free operation of the computer, reducing overall hardware costs by a third, and reducing the hardware costs for building an ALU processor by 2.5 times.

Pages: 12-22
References
  1. Grebeshkov A.Yu. Mikroprotsessornye sistemy i programmnoe obespechenie v sredstvakh svyazi. Samara. PGUTI. 2009. 298 s.
  2. Glushko A.A., Zinchenko L.A., Shakhnov V.A. Modelirovanie vozdeistviya tyazhelykh zaryazhennykh chastits na kharakteristiki polevykh tranzistorov struktury «kremnii na izolyatore». Radiotekhnika i elektronika. 2015. T. 60. № 10. S. 1090−1096. DOI: 10.7868/S0033849415070074.
  3. Meshcheryakov S.A., Berdyshev A.V. Elektroteplovaya model vozdeistviya elektromagnitnogo izlucheniya na poluprovodnikovye struktury. Radiotekhnika i elektronika. 2013. T. 58. №: 11. S. 1127−1133. DOI: 10.7868/S0033849413110119.
  4. Naseer R. and Draper J. Parallel Double Error Correcting Code Design to Mitigate Multi-Bit Upsets in SRAMs. Information Sciences Institute University of Southern California, IEEE Trans. Device Mater. 2008. V. 6. P. 222−225.
  5. Frank Hall Schmidt, Jr. Fault. Tolerant Design Implementation on Radiation Hardened By Design SRAM-Based FPGAs. Electrical Engineering United States Air Force Academy Submitted to the Department of Aeronautics and Astronauticsin partial ful. 2011. 306 p.
  6. Shcherbakov N.S. Dostovernost raboty tsifrovykh ustroistv. M.: Mashinostroenie.1989. 224 s.
  7. Bashkirov A.V., Muratov A.V., Suslova O.E. Obzornyi analiz pomekhoustoichivogo kodirovaniya v tsifrovykh sistemakh peredachi dannykh. Radiotekhnika. 2016. № 6. S. 31−35.
  8. Zolotarev V.V., Ovechkin G.V. Novye sredstva korrektsii oshibok dlya vysokoskorostnoi peredachi i khraneniya dannykh. Radiotekhnika. 2016. № 8. S. 104−109.
  9. Pavlov A.A., Tsarkov A.N., Pavlov P.A., Gusev K.V., Gusev A.V. Sorokin D.E., Lasyak M.I. Metod pomekhoustoichivogo kodirovaniya informatsii kanalov peredachi dannykh teleizmeritelnykh informatsionnykh sistem s korrektsiei oshibok v dvukh baitakh informatsii. Izmeritelnaya tekhnika. 2014. № 7. S. 10−15.
  10. Pavlov A.A., Tsarkov A.N., Pavlov P.A., Sorokin D.E., Gusev A.V. Lasyak M.I. Metod pomekhoustoichivogo kodirovaniya informatsii kanalov peredachi dannykh s ispravleniem oshibok v dvukh baitakh informatsii. Vestnik kompyuternykh i informatsionnykh tekhnologii. 2015. № 1. S. 15−21.
  11. Reviriego P., Flanagan M., Maestro J.A. A (64,45) Triple Error Correction Code for Memory Applications. IEEE Trans. Device Mater. Rel. March 2012. V. 12. № 1. P. 101−106.
  12. Veronese G.S., Correia M., Bessani A.N., Lung L.C., and Verissimo P. Efficient Byzantine fault-tolerance. IEEE Transactions on Computers. 2013. P. 21−27.
  13. Luiz A.F., Lung L.C., Correia M. MITRA: Byzantine Fault-Tolerant Middleware for Transaction Processing on Replicated Databases. SIGMOD Record. March 2014. V. 43. № 1. P. 14−20.
  14. Pavlov A.A., Tsarkov A.N., Pavlov P.A., Korsunskii D.A. Metod obnaruzheniya oshibok v ustroistvakh khraneniya i peredachi informatsii. Radiotekhnika. 2017. № 3. S. 50−58.
Date of receipt: 12 декабря 2019 г.