Yu.S. Balashov – Dr.Sc.(Phys.-Math.), Professor, 

Department «Radio Electronic Devices and Systems», Voronezh State Technical University

A.A. Pirogov – Ph.D.(Eng.), Associate Professor, 

Department Radio Equipment Engineering and Manufacturing, Voronezh State Technical University E-mail: pirogov.alx@gmail.com

Programmable logic integrated circuits (FPGAs) are widely used in the electronics industry. FPGAs are integrated circuits with variable (programmable) structures, are the most promising at the moment, they are distinguished by a high degree of universality, low development costs and low design time. They can be used to build reconfigurable systems, as well as in problems of logical emulation. In this work, we carried out a simulation of the structure, time analysis and performance evaluation of binary adders performed according to various implementation schemes.

Multi-bit adders are built on the basis of single-bit, and the implementation of schemes is possible, both with cascade connection, and with the use of accelerated transfer blocks. In order to obtain a multi-digit adder, it is sufficient to connect the inputs and outputs of the translations of the corresponding binary digits. Such a cascade connection of adders leads to a significant decrease in speed.

To speed up the process of addition apply the scheme of accelerated transfer. In this case, any transfer from the previous discharge can be expressed as a logical function of lower-order variables, and the computation time of such a function will be less than passing the transfer through the adder.

As a result of the study, the models of four-digit adders made according to a cascade scheme and an accelerated transfer scheme were obtained. The simulation was carried out in the Xilinx ISE software package using the built-in circuit editor, as well as the programming shell in the Verilog language. The resulting time diagrams of adders for the same set of numbers are the same, which confirms the correct structure of devices. Physical verification of the modules was carried out on the basis of the Spilean 3E Digilent debug board. Received response time data of adders, which confirm the higher performance indicators of the scheme with accelerated transfer.

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